Intel

Cyclone® II Field Programmable Gate Array (FPGA) IC 142 119808 4608 208-BFQFP

Introduction

Following the immensely successful first-generation Cyclone® device

family, Altera® Cyclone II FPGAs extend the low-cost FPGA density

range to 68,416 logic elements (LEs) and provide up to 622 usable I/O

pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are

manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric

process to ensure rapid availability and low cost. By minimizing silicon

area, Cyclone II devices can support complex digital systems on a single

chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who

compromise power consumption and performance for low-cost, 

Altera’s latest generation of low-cost FPGAs—Cyclone II FPGAs, offer 60% 

higher performance and half the power consumption of competing 90-nm FPGAs. 

The low cost and optimized feature set of Cyclone II FPGAs make them ideal 

solutions for a wide array of automotive, consumer,communications, video processing, 

test and measurement, and other end-market solutions. Reference designs, 

system diagrams, and IP, found at www.altera.com, are available to help

 you rapidly develop complete end-market solutions using Cyclone II FPGAs.

Low-Cost Embedded Processing Solutions

Cyclone II devices support the Nios II embedded processor which allows

you to implement custom-fit embedded processing solutions. Cyclone II

devices can also expand the peripheral set, memory, I/O, or performance

of embedded processors. Single or multiple Nios II embedded processors

can be designed into a Cyclone II device to provide additional

co-processing power or even replace existing embedded processors in

your system. Using Cyclone II and Nios II together allow for low-cost,

high-performance embedded processing solutions, which allow you to

extend your product's life cycle and improve time to market over

standard product solutions.

Low-Cost DSP Solutions

Use Cyclone II FPGAs alone or as DSP co-processors to improve

price-to-performance ratios for digital signal processing (DSP)

applications. You can implement high-performance yet low-cost DSP

systems with the following Cyclone II features and design support:

■ Up to 150 18 × 18 multipliers

■ Up to 1.1 Mbit of on-chip embedded memory

■ High-speed interfaces to external memory

■ DSP intellectual property (IP) cores

■ DSP Builder interface to The Mathworks Simulink and Matlab

design environment

■ DSP Development Kit, Cyclone II Edition

Cyclone II devices include a powerful FPGA feature set optimized for

low-cost applications including a wide range of density, memory,

embedded multiplier, and packaging options. Cyclone II devices

 support a wide range of common external memory interfaces and 

I/O protocols required in low-cost applications. Parameterizable IP cores 

from Altera and partners make using Cyclone II interfaces and protocols fast and easy

Features

The Cyclone II device family offers the following features:

■ High-density architecture with 4,608 to 68,416 LEs

● M4K embedded memory blocks

● Up to 1.1 Mbits of RAM available without reducing available

logic

● 4,096 memory bits per block (4,608 bits per block including 512

parity bits)

● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,

and ×36

● True dual-port (one read and one write, two reads, or two

writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

● Byte enables for data input masking during writes

● Up to 260-MHz operation

■ Embedded multipliers

● Up to 150 18- × 18-bit multipliers are each configurable as two

independent 9- × 9-bit multipliers with up to 250-MHz

performance

● Optional input and output registers

■ Advanced I/O support

● High-speed differential I/O standard support, including LVDS,

RSDS, mini-LVDS, LVPECL, differential HSTL, and differential

SSTL

● Single-ended I/O standard support, including 2.5-V and 1.8-V,

SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI

and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,

and 1.8-V LVTTL

● Peripheral Component Interconnect Special Interest Group (PCI

SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V

operation at 33 or 66 MHz for 32- or 64-bit interfaces

● PCI Express with an external TI PHY and an Altera PCI Express

×1 Megacore® function

● 133-MHz PCI-X 1.0 specification compatibility

● High-speed external memory support, including DDR, DDR2,

and SDR SDRAM, and QDRII SRAM supported by drop in

Altera IP MegaCore functions for ease of use

● Three dedicated registers per I/O element (IOE): one input

register, one output register, and one output-enable register

● Programmable bus-hold feature

● Programmable output drive strength feature

● Programmable delays from the pin to the IOE or logic array

● I/O bank grouping for unique VCCIO and/or VREF bank

settings

● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and

3.3-interfaces

● Hot-socketing operation support

● Tri-state with weak pull-up on I/O pins before and during

configuration

● Programmable open-drain outputs

● Series on-chip termination support

■ Flexible clock management circuitry

● Hierarchical clock network for up to 402.5-MHz performance

● Up to four PLLs per device provide clock multiplication and

division, phase shifting, programmable duty cycle, and external

clock outputs, allowing system-level clock management and

skew control

● Up to 16 global clock lines in the global clock network that drive

throughout the entire device

■ Device configuration

● Fast serial configuration allows configuration times less than

100 ms

● Decompression feature allows for smaller programming file

storage and faster configuration times

● Supports multiple configuration modes: active serial, passive

serial, and JTAG-based configuration

● Supports configuration through low-cost serial configuration

devices

● Device configuration supports multiple voltages (either 3.3, 2.5,

or 1.8 V)

■ Intellectual property

● Altera megafunction and Altera MegaCore function support,

and Altera Megafunctions Partners Program (AMPPSM)

megafunction support, for a wide range of embedded

processors, on-chip and off-chip interfaces, peripheral

functions, DSP functions, and communications functions and 

protocols. Visit the Altera IPMegaStore at www.altera.com to

download IP MegaCore functions.

● Nios II Embedded Processor support

The Cyclone II family offers devices with the Fast-On feature, which

offers a faster power-on-reset (POR) time. Devices that support the

Fast-On feature are designated with an “A” in the device ordering code.For example, 

EP2C5A, EP2C8A, EP2C15A, and EP2C20A. The EP2C5A is only available in the automotive speed grade. 

The EP2C8A and EP2C20A are only available in the industrial speed grade. 

The EP2C15A is only available with the Fast-On feature and is available in both commercial and industrial grades. 

The Cyclone II “A” devices are identical in feature set and functionality to the non-A devices except for support of the faster POR time.

Cyclone II A devices are offered in automotive speed grade. For more

information, refer to the Cyclone II section in the Automotive-Grade Device Handbook.

For more information on POR time specifications for Cyclone II A and

non-A devices, refer to the Hot Socketing & Power-On Reset chapter in the Cyclone II Device Handbook.

Table 1–1 lists the Cyclone II device family features. Table 1–2 lists the

Cyclone II device package offerings and maximum user I/O pins.

How to choose FPGA for your project?

PDF

Cyclone® II Field Programmable Gate Array (FPGA) IC 315 239616 18752 484-BGA

Introduction

Following the immensely successful first-generation Cyclone® device

family, Altera® Cyclone II FPGAs extend the low-cost FPGA density

range to 68,416 logic elements (LEs) and provide up to 622 usable I/O

pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are

manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric

process to ensure rapid availability and low cost. By minimizing silicon

area, Cyclone II devices can support complex digital systems on a single

chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who

compromise power consumption and performance for low-cost, 

Altera’s latest generation of low-cost FPGAs—Cyclone II FPGAs, offer 60% 

higher performance and half the power consumption of competing 90-nm FPGAs. 

The low cost and optimized feature set of Cyclone II FPGAs make them ideal 

solutions for a wide array of automotive, consumer,communications, video processing, 

test and measurement, and other end-market solutions. Reference designs, 

system diagrams, and IP, found at www.altera.com, are available to help

 you rapidly develop complete end-market solutions using Cyclone II FPGAs.

Low-Cost Embedded Processing Solutions

Cyclone II devices support the Nios II embedded processor which allows

you to implement custom-fit embedded processing solutions. Cyclone II

devices can also expand the peripheral set, memory, I/O, or performance

of embedded processors. Single or multiple Nios II embedded processors

can be designed into a Cyclone II device to provide additional

co-processing power or even replace existing embedded processors in

your system. Using Cyclone II and Nios II together allow for low-cost,

high-performance embedded processing solutions, which allow you to

extend your product's life cycle and improve time to market over

standard product solutions.

Low-Cost DSP Solutions

Use Cyclone II FPGAs alone or as DSP co-processors to improve

price-to-performance ratios for digital signal processing (DSP)

applications. You can implement high-performance yet low-cost DSP

systems with the following Cyclone II features and design support:

■ Up to 150 18 × 18 multipliers

■ Up to 1.1 Mbit of on-chip embedded memory

■ High-speed interfaces to external memory

■ DSP intellectual property (IP) cores

■ DSP Builder interface to The Mathworks Simulink and Matlab

design environment

■ DSP Development Kit, Cyclone II Edition

Cyclone II devices include a powerful FPGA feature set optimized for

low-cost applications including a wide range of density, memory,

embedded multiplier, and packaging options. Cyclone II devices

 support a wide range of common external memory interfaces and 

I/O protocols required in low-cost applications. Parameterizable IP cores 

from Altera and partners make using Cyclone II interfaces and protocols fast and easy

Features

The Cyclone II device family offers the following features:

■ High-density architecture with 4,608 to 68,416 LEs

● M4K embedded memory blocks

● Up to 1.1 Mbits of RAM available without reducing available

logic

● 4,096 memory bits per block (4,608 bits per block including 512

parity bits)

● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,

and ×36

● True dual-port (one read and one write, two reads, or two

writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

● Byte enables for data input masking during writes

● Up to 260-MHz operation

■ Embedded multipliers

● Up to 150 18- × 18-bit multipliers are each configurable as two

independent 9- × 9-bit multipliers with up to 250-MHz

performance

● Optional input and output registers

■ Advanced I/O support

● High-speed differential I/O standard support, including LVDS,

RSDS, mini-LVDS, LVPECL, differential HSTL, and differential

SSTL

● Single-ended I/O standard support, including 2.5-V and 1.8-V,

SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI

and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,

and 1.8-V LVTTL

● Peripheral Component Interconnect Special Interest Group (PCI

SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V

operation at 33 or 66 MHz for 32- or 64-bit interfaces

● PCI Express with an external TI PHY and an Altera PCI Express

×1 Megacore® function

● 133-MHz PCI-X 1.0 specification compatibility

● High-speed external memory support, including DDR, DDR2,

and SDR SDRAM, and QDRII SRAM supported by drop in

Altera IP MegaCore functions for ease of use

● Three dedicated registers per I/O element (IOE): one input

register, one output register, and one output-enable register

● Programmable bus-hold feature

● Programmable output drive strength feature

● Programmable delays from the pin to the IOE or logic array

● I/O bank grouping for unique VCCIO and/or VREF bank

settings

● MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and

3.3-interfaces

● Hot-socketing operation support

● Tri-state with weak pull-up on I/O pins before and during

configuration

● Programmable open-drain outputs

● Series on-chip termination support

■ Flexible clock management circuitry

● Hierarchical clock network for up to 402.5-MHz performance

● Up to four PLLs per device provide clock multiplication and

division, phase shifting, programmable duty cycle, and external

clock outputs, allowing system-level clock management and

skew control

● Up to 16 global clock lines in the global clock network that drive

throughout the entire device

■ Device configuration

● Fast serial configuration allows configuration times less than

100 ms

● Decompression feature allows for smaller programming file

storage and faster configuration times

● Supports multiple configuration modes: active serial, passive

serial, and JTAG-based configuration

● Supports configuration through low-cost serial configuration

devices

● Device configuration supports multiple voltages (either 3.3, 2.5,

or 1.8 V)

■ Intellectual property

● Altera megafunction and Altera MegaCore function support,

and Altera Megafunctions Partners Program (AMPPSM)

megafunction support, for a wide range of embedded

processors, on-chip and off-chip interfaces, peripheral

functions, DSP functions, and communications functions and 

protocols. Visit the Altera IPMegaStore at www.altera.com to

download IP MegaCore functions.

● Nios II Embedded Processor support

The Cyclone II family offers devices with the Fast-On feature, which

offers a faster power-on-reset (POR) time. Devices that support the

Fast-On feature are designated with an “A” in the device ordering code.For example, 

EP2C5A, EP2C8A, EP2C15A, and EP2C20A. The EP2C5A is only available in the automotive speed grade. 

The EP2C8A and EP2C20A are only available in the industrial speed grade. 

The EP2C15A is only available with the Fast-On feature and is available in both commercial and industrial grades. 

The Cyclone II “A” devices are identical in feature set and functionality to the non-A devices except for support of the faster POR time.

Cyclone II A devices are offered in automotive speed grade. For more

information, refer to the Cyclone II section in the Automotive-Grade Device Handbook.

For more information on POR time specifications for Cyclone II A and

non-A devices, refer to the Hot Socketing & Power-On Reset chapter in the Cyclone II Device Handbook.

Table 1–1 lists the Cyclone II device family features. Table 1–2 lists the

Cyclone II device package offerings and maximum user I/O pins.

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® III Field Programmable Gate Array (FPGA) IC 94 423936 10320 144-LQFP Exposed Pad

Cyclone III Device Family Overview

Cyclone® III device family offers a unique combination of high functionality, low

power and low cost. Based on Taiwan Semiconductor Manufacturing Company

(TSMC) low-power (LP) process technology, silicon optimizations and software

features to minimize power consumption, Cyclone III device family provides the ideal

solution for your high-volume, low-power, and cost-sensitive applications. To address

the unique design needs, Cyclone III device family offers the following two variants:

■ Cyclone III—lowest power, high functionality with the lowest cost

■ Cyclone III LS—lowest power FPGAs with security

With densities ranging from about 5,000 to 200,000 logic elements (LEs) and

0.5 Megabits (Mb) to 8 Mb of memory for less than ¼ watt of static power

consumption, Cyclone III device family makes it easier for you to meet your power

budget. Cyclone III LS devices are the first to implement a suite of security features at

the silicon, software, and intellectual property (IP) level on a low-power and

high-functionality FPGA platform. This suite of security features protects the IP from

tampering, reverse engineering and cloning. In addition, Cyclone III LS devices

support design separation which enables you to introduce redundancy in a single

chip to reduce size, weight, and power of your application.

Cyclone III Device Family Features

Cyclone III device family offers the following features:

Lowest Power FPGAs

■ Lowest power consumption with TSMC low-power process technology and

Altera® power-aware design flow

■ Low-power operation offers the following benefits:

■ Extended battery life for portable and handheld applications

■ Reduced or eliminated cooling system costs

■ Operation in thermally-challenged environments

■ Hot-socketing operation support

Design Security Feature

Cyclone III LS devices offer the following design security features:

■ Configuration security using advanced encryption standard (AES) with 256-bit

volatile key

■ Routing architecture optimized for design separation flow with the Quartus® II

software

■ Design separation flow achieves both physical and functional isolation

between design partitions

■ Ability to disable external JTAG port

■ Error Detection (ED) Cycle Indicator to core

■ Provides a pass or fail indicator at every ED cycle

■ Provides visibility over intentional or unintentional change of configuration

random access memory (CRAM) bits

■ Ability to perform zeroization to clear contents of the FPGA logic, CRAM,

embedded memory, and AES key

■ Internal oscillator enables system monitor and health check capabilities

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® IV E Field Programmable Gate Array (FPGA) IC 89 516096 15408 164-TFBGA

Operating Conditions

When Cyclone IV devices are implemented in a system, they are rated according to a

set of defined parameters. To maintain the highest possible performance and

reliability of Cyclone IV devices, you must consider the operating requirements

described in this chapter.

Cyclone IV devices are offered in commercial, industrial, extended industrial and,

automotive grades. Cyclone IV E devices offer –6 (fastest), –7, –8, –8L, and –9L speed

grades for commercial devices, –8L speed grades for industrial devices, and –7 speed

grade for extended industrial and automotive devices. Cyclone IV GX devices offer

–6 (fastest), –7, and –8 speed grades for commercial devices and –7 speed grade for

industrial devices.

Cyclone IV E devices are offered in core voltages of 1.0 and 1.2 V. Cyclone IV E

devices with a core voltage of 1.0 V have an ‘L’ prefix attached to the speed grade.

In this chapter, a prefix associated with the operating temperature range is attached to

the speed grades; commercial with a “C” prefix, industrial with an “I” prefix, and

automotive with an “A” prefix. Therefore, commercial devices are indicated as C6, C7,

C8, C8L, or C9L per respective speed grade. Industrial devices are indicated as I7, I8,

or I8L. Automotive devices are indicated as A7.

Cyclone IV E industrial devices I7 are offered with extended operating temperature range.

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® IV E Field Programmable Gate Array (FPGA) IC 328 1161216 39600 484-BGA

Operating Conditions

When Cyclone IV devices are implemented in a system, they are rated according to a

set of defined parameters. To maintain the highest possible performance and

reliability of Cyclone IV devices, you must consider the operating requirements

described in this chapter.

Cyclone IV devices are offered in commercial, industrial, extended industrial and,

automotive grades. Cyclone IV E devices offer –6 (fastest), –7, –8, –8L, and –9L speed

grades for commercial devices, –8L speed grades for industrial devices, and –7 speed

grade for extended industrial and automotive devices. Cyclone IV GX devices offer

–6 (fastest), –7, and –8 speed grades for commercial devices and –7 speed grade for

industrial devices.

Cyclone IV E devices are offered in core voltages of 1.0 and 1.2 V. Cyclone IV E

devices with a core voltage of 1.0 V have an ‘L’ prefix attached to the speed grade.

In this chapter, a prefix associated with the operating temperature range is attached to

the speed grades; commercial with a “C” prefix, industrial with an “I” prefix, and

automotive with an “A” prefix. Therefore, commercial devices are indicated as C6, C7,

C8, C8L, or C9L per respective speed grade. Industrial devices are indicated as I7, I8,

or I8L. Automotive devices are indicated as A7.

Cyclone IV E industrial devices I7 are offered with extended operating temperature range.

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® IV GX Field Programmable Gate Array (FPGA) IC 270 6635520 149760 484-BGA

Introduction

The CycloneTM field programmable gate array family is based ona 1.5-V,

0.13-um, alayer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,

32-bit peripheral component interconnect (PCI), for interfacing with and

supporting ASSP and ASIC devices. Altera also offers new low-cost serial

configuration devices to configure Cyclone devices.

Features

■Up to 294,912 RAM bits (36,864 bytes)

■Supports configuration through low-cost serial configuration device

■Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■Support for 66-MHz, 32-bit PCI standard

■Low speed (311 Mbps) LVDS 1/O support

■Up to two PLLs per device provide clock multiplication and phase shifting

■Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■Support for external memory, induding DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■Support for multiple intellectual property (IP) cores, including

Altera" MegaCore functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions

Cyclone® IV GX Field Programmable Gate Array (FPGA) IC 310 2562048 49888 672-BGA

Introduction

The CycloneTM field programmable gate array family is based ona 1.5-V,

0.13-um, alayer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,

32-bit peripheral component interconnect (PCI), for interfacing with and

supporting ASSP and ASIC devices. Altera also offers new low-cost serial

configuration devices to configure Cyclone devices.

Features

■Up to 294,912 RAM bits (36,864 bytes)

■Supports configuration through low-cost serial configuration device

■Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■Support for 66-MHz, 32-bit PCI standard

■Low speed (311 Mbps) LVDS 1/O support

■Up to two PLLs per device provide clock multiplication and phase shifting

■Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

■Support for external memory, induding DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

■Support for multiple intellectual property (IP) cores, including

Altera" MegaCore functions and Altera Megafunctions Partners

Program (AMPPSM) megafunctions

Chip Altera Cyclone naming rules，Chinese chip Will replace it

PDF

Cyclone® V E Field Programmable Gate Array (FPGA) IC 224 14251008 301000 484-BGA

Summary of Features for Cyclone V Devices

Technology

• TSMC's 28-nm low-power (28LP) process technology

• 1.1 V core voltage

Packaging

• Wirebond low-halogen packages

• Multiple device densities with compatible package footprints for seamless migration between

different device densities

• RoHS-compliant and leaded(1)options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

• M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)

• Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%

of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

• Native support for up to three signal processing precision levels

(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same

variable-precision DSP block

• 64-bit accumulator and cascade

• Embedded internal coefficient memory

• Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with

multifunction support, endpoint, and root port

Clock networks

• Up to 550 MHz global clock network

• Global, quadrant, and peripheral clock networks

• Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

• Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)

• Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

• 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter

• 400 MHz/800 Mbps external memory interface

• On-chip termination (OCT)

• 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

• 614 Mbps to 6.144 Gbps integrated transceiver speed

• Transmit pre-emphasis and receiver equalization

• Dynamic partial reconfiguration of individual channels

HPS(Cyclone V SE, SX,and ST devices only)

• Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with

support for symmetric and asymmetric multiprocessing

• Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0

On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND

flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area

network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO

interfaces

• System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)

controller, FPGA configuration manager, and clock and reset managers

• On-chip RAM and boot ROM

• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA

bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa

• FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport

front end (MPFE) of the HPS SDRAM controller

• Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

• Tamper protection—comprehensive design protection to protect your valuable IP investments

• Enhanced advanced encryption standard (AES) design security features

• CvP

• Dynamic reconfiguration of the FPGA

• Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and

x16 configuration options

• Internal scrubbing (2)

• Partial reconfiguration (3)