Lattice Semiconductor Corporation

iCE40™ LP Field Programmable Gate Array (FPGA) IC 63 131072 7680 81-VFBGA

General Description

The iCE40 family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs, Nonvolatile

Programmable Configuration Memory (NVCM) and blocks of sysMEM™ Embedded Block RAM (EBR) surrounded by

Programmable I/O (PIO). 

The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with

rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the

device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs

utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The

blocks are connected with many vertical and horizontal routing channel resources. Theplace and route software tool

automatically allocates these routing resources.

In the iCE40 family, there are up to four independent sysIO banks. Note on some packages VCCIO banks are tied together.

There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document.

The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO.

The iCE40 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have multiply, divide,

and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks.

Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 includes

on-chip, Nonvolatile Configuration Memory (NVCM).

Features

• Flexible Logic Architecture

      Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os

• Ultra Low Power Devices

      Advanced 40 nm low power process

      As low as 21 µA standby power

      Programmable low swing differential I/Os

• Embedded and Distributed Memory

      Up to 128 kbits sysMEM™ Embedded Block RAM

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

• High Current LED Drivers

      Three High Current Drivers used for three different LEDs or one RGB LED

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      — LVCMOS 3.3/2.5/1.8

      — LVDS25E, subLVDS

      — Schmitt trigger inputs, to 200 mV typical hysteresis

      Programmable pull-up mode

• Flexible On-Chip Clocking

      Eight low-skew global clock resources

      Up to two analog PLLs per device

• Flexible Device Configuration

      SRAM is configured through:

      — Standard SPI Interface

      — Internal Nonvolatile Configuration Memory (NVCM)

• Broad Range of Package Options

      WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA,and csBGA package options

      Small footprint package options

      — As small as 1.40 mm x 1.48 mm

      Advanced halogen-free packaging

MachXO Field Programmable Gate Array (FPGA) IC 78 256 100-LQFP

General Description

The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices

in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). 

The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column

to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize

a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-face standards. The

blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool

automatically allocates these routing resources.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-tions. The

PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are

optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in

a two-dimensional array. Only one type of block is used per row.

In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on dif-ferent

Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these

blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes

dedicated FIFO pointer and flag“hard”control logic to minimize LUT use.

The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured,

the device enters into user mode with these registers SET/RESET according to the configuration set-ting, allowing device

entering to a known state for predictable system function.

The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices.These blocks

are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are

used to manage the frequency and phase relationships of the clocks.

Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to

the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing

easy integration into the overall system.

Features

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single chip, no external configuration memory required

      Excellent design security, no bit stream to intercept

      Reconfigure SRAM based logic in milliseconds

      SRAM and non-volatile memory programmable through JTAG port

      Supports background programming of non-volatile memory

• Sleep Mode

      Allows up to 100x static current reduction

• TransFR™ Reconfiguration (TFR)

      In-field logic update while system operates

• High I/O to Logic Density

      256 to 2280 LUT4s

      73 to 271 I/Os with extensive package options

      Density migration supported

      Lead free/RoHS compliant packaging

• Embedded and Distributed Memory

      Up to 27.6 Kbits sysMEM™ Embedded Block RAM

      Up to 7.7 Kbits distributed RAM

      Dedicated FIFO control logic

• Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      ——LVCMOS 3.3/2.5/1.8/1.5/1.2

      ——LVTTL

      ——PCI

      ——LVDS, Bus-LVDS, LVPECL, RSDS

• sysCLOCK™ PLLs

      Up to two analog PLLs per device

      Clock multiply, divide, and phase shifting

• System Level Support

      IEEE Standard 1149.1 Boundary Scan

      Onboard oscillator

      Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply

      IEEE 1532 compliant in-system programming

How to choose FPGA for your project?

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