Microsemi Corporation

ProASIC3 Field Programmable Gate Array (FPGA) IC 80 18432 132-WFQFN

General Description

ProASIC3，the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those

of the ProASIC^PLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low

power, single-chip solution that is Instant On. ProASIC3 is reprogrammable and offers time-to-market benefits at an

ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning

circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support.

ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to

300 user I/Os.

ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi ordering numbers

that begin with M1A3P (Cortex-M1) and do not support AES decryption.

Features and Benefits

• High Capacity

      15 K to 1 M System Gates

      Up to 144 Kbits of True Dual-Port SRAM

      Up to 300 User I/Os

• Reprogrammable Flash Technology

      130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

      Instant On Level 0 Support

      Single-Chip Solution

      Retains Programmed Design when Powered Off

• High Performance

      350 MHz System Performance

      3.3 V, 66 MHz 64-Bit PCI

• In-System Programming (ISP) and Security

      ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3

      devices) via JTAG (IEEE 1532-compliant)

      FlashLock® to Secure FPGA Contents

• Low Power

      Core Voltage for Low Power

      Support for 1.5V-Only Systems

      Low-Impedance Flash Switches

• High-Performance Routing Hierarchy

      Segmented, Hierarchical Routing and Clock Structure

• Advanced I/O

      700 Mbps DDR,LVDS-Capable I/Os (A3P250 and above)

      1.5V, 1.8 V, 2.5 V,and 3.3V Mixed-Voltage Operation

      Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V

      Bank-Selectable I/O Voltages—up to 4 Banks per Chip

      Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V / 2.5V / 1.8V / 1.5V, 3.3V PCI / 3.3V PCI-X and LVCMOS 2.5V / 5.0V

      Input

      Differential I/O Standards: LVPECL，LVDS，B-LVDS, and M-LVDS (A3P250 and above)

      I/O Registers on Input, Output, and Enable Paths

      Hot-Swappable and Cold Sparing I/Os

      Programmable Output Slew Rate and Drive Strength

      Weak Pull-Up/-Down

      IEEE 1149.1 (JTAG) Boundary Scan Test

      Pin-Compatible Packages across the ProASIC3 Family

• Clock Conditioning Circuit (CCC) and PLL

      Six CCC Blocks, One with an Integrated PLL

      Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

      Wide Input Frequency Range (1.5 MHz to 350 MHz)

• Embedded Memory

      1 Kbit of FlashROM User Nonvolatile Memory

      SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations)

      True Dual-Port SRAM (except x18)

• ARM Processor Support in ProASIC3 FPGAs

      M1 ProASIC3 Devices-ARM®Cortex®-M1 Soft Processor Available with or without Debug

How to choose FPGA for your project?

PDF

ProASIC3L Field Programmable Gate Array (FPGA) IC 157 36864 256-LBGA

Clock Frequency Synthesis

Deriving clocks of various frequencies from a single reference clock is known as frequency synthesis.The PLL has an input

frequency range from 1.5 to 350 MHz. This frequency is automatically divideddown to a range between 1.5 MHz and

5.5 MHz by input dividers (not shown in Figure 4-19 on page 100)between PLL macro inputs and PLL phase detector

inputs. The VCO output is capable of an outputrange from 24 to 350 MHz. With dividers before the input to the PLL core

and following the VCO outputs,the VCO output frequency can be divided to provide the final frequency range from 0.75

to 350 MHz.Using SmartGen, the dividers are automatically set to achieve the closest possible matches to thespecified

output frequencies.

Users should be cautious when selecting the desired PLL input and output frequencies and the I/O bufferstandard used

to connect to the PLL input and output clocks. Depending on the I/O standards used forthe PLL input and output clocks,

the I/O frequencies have different maximum limits. Refer to the familydatasheets for specifications of maximum I/O

frequencies for supported I/O standards. Desired PLL inputor output frequencies will not be achieved if the selected

frequencies are higher than the maximum I/Ofrequencies allowed by the selected I/O standards. Users should be careful

when selecting the I/Ostandards used for PLL input and output clocks. Performing post-layout simulation can help detect

thistype of error, which will be identified with pulse width violation errors. Users are strongly encouraged toperform

post-layout simulation to ensure the I/O standard used can provide the desired PLL input oroutput frequencies. Users can

also choose to cascade PLLs together to achieve the high frequenciesneeded for their applications. Details of cascading

PLLs are discussed in the "Cascading CCCs" sectionon page 125.

In SmartGen, the actual generated frequency (under typical operating conditions) will be displayedbeside the requested

output frequency value. This provides the ability to determine the exact frequencythat can be generated by SmartGen, in

real time. The log file generated by SmartGen is a useful tool indetermining how closely the requested clock frequencies

match the user specifications. For example,assume a user specifies 101 MHz as one of the secondary output frequencies.

If the best outputfrequency that could be achieved were 100 MHz, the log file generated by SmartGen would indicate

theactual generated frequency

How to choose FPGA for your project?

PDF

ProASIC3 Field Programmable Gate Array (FPGA) IC 194 55296 484-BGA

General Description

ProASIC3，the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those

of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low

power, single-chip solution that is Instant On. ProASIC3 is reprogrammable and offers time-to-market benefits at an

ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning

circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support.

ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to

300 user I/Os.

ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi ordering numbers

that begin with M1A3P (Cortex-M1) and do not support AES decryption.

Features and Benefits

• High Capacity

      15 K to 1 M System Gates

      Up to 144 Kbits of True Dual-Port SRAM

      Up to 300 User I/Os

• Reprogrammable Flash Technology

      130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

      Instant On Level 0 Support

      Single-Chip Solution

      Retains Programmed Design when Powered Off

• High Performance

      350 MHz System Performance

      3.3 V, 66 MHz 64-Bit PCI

• In-System Programming (ISP) and Security

      ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3

      devices) via JTAG (IEEE 1532-compliant)

      FlashLock® to Secure FPGA Contents

• Low Power

      Core Voltage for Low Power

      Support for 1.5V-Only Systems

      Low-Impedance Flash Switches

• High-Performance Routing Hierarchy

      Segmented, Hierarchical Routing and Clock Structure

• Advanced I/O

      700 Mbps DDR,LVDS-Capable I/Os (A3P250 and above)

      1.5V, 1.8 V, 2.5 V,and 3.3V Mixed-Voltage Operation

      Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V

      Bank-Selectable I/O Voltages—up to 4 Banks per Chip

      Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V / 2.5V / 1.8V / 1.5V, 3.3V PCI / 3.3V PCI-X and LVCMOS 2.5V / 5.0V

      Input

      Differential I/O Standards: LVPECL，LVDS，B-LVDS, and M-LVDS (A3P250 and above)

      I/O Registers on Input, Output, and Enable Paths

      Hot-Swappable and Cold Sparing I/Os

      Programmable Output Slew Rate and Drive Strength

      Weak Pull-Up/-Down

      IEEE 1149.1 (JTAG) Boundary Scan Test

      Pin-Compatible Packages across the ProASIC3 Family

• Clock Conditioning Circuit (CCC) and PLL

      Six CCC Blocks, One with an Integrated PLL

      Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback

      Wide Input Frequency Range (1.5 MHz to 350 MHz)

• Embedded Memory

      1 Kbit of FlashROM User Nonvolatile Memory

      SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations)

      True Dual-Port SRAM (except x18)

• ARM Processor Support in ProASIC3 FPGAs

      M1 ProASIC3 Devices-ARM®Cortex®-M1 Soft Processor Available with or without Debug

How to choose FPGA for your project?