NXP USA Inc.

56800E 56F8xxx Microcontroller IC 16-Bit 32MHz 16KB (8K x 16) FLASH 32-LQFP (7x7)                             

Overview

Product Description

The 56F8013/56F8011 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8013/56F8011 is well-suited for many applications. 

The 56F8013/56F8011 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general purpose inverters, smart sensors, fire and security systems, switched mode power supply, power management, and medical monitoring applications.

The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle.  The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications.

The 56F8013/56F8011 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8013/56F8011 also offers up to 26 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F8013 Digital Signal Controller includes 16KB of Program Flash and 4KB of Unified Data/Program RAM. The 56F8011 Digital Signal Controller includes 12KB of Program Flash and 2KB of Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages. Program Flash page erase size is 512 Bytes (256 Words).

A full set of programmable peripherals—PWM, ADCs, SCI, SPI, I2C, Quad Timer—supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).

Device Description

• Up to 32 MIPS at 32MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• 56F8013 device offers 16KB Program Flash

56F8011 device offers 12KB Program Flash

• 56F8013 device offers 4KB Unified Data/Program RAM

56F8011 device offers 2KB Unified Data/Program RAM

• One 6-channel PWM module

• Two 3-channel 12-bit ADCs

• One Serial Communication Interface (SCI) with LIN slave functionality

• One Serial Peripheral Interface (SPI)

• One 16-bit Quad Timer

• One Inter-Integrated Circuit (I2 C) Port

• Computer Operating Properly (COP)/Watchdog

• On-Chip Relaxation Oscillator

• Integrated Power-On Reset and Low-Voltage Interrupt Module

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging

• Up to 26 GPIO lines

• 32-pin LQFP Package 

Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging

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