NXP USA Inc.

HCS12X HCS12X Microcontroller IC 16-Bit 50MHz 256KB (256K x 8) FLASH 80-QFP (14x14)

Introduction

The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including

new features for enhanced system integrity and greater functionality. These new features include a

Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with

enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency

modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product

range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship

MC9S12XE100.

The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit

MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently

enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of

compatibility between the S12XE and S12XD families.

The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor

which is programmable in “C” language and runs at twice the bus frequency of the S12X with an

instruction set optimized for data movement, logic and bit manipulation instructions and which can service

any peripheral module on the device. The new enhanced version has improved interrupt handling

capability and is fully compatible with the existing XGATE module.

The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM,

eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-

channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an 8-

channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12),

two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit

standard timer module (TIM).

The MC9S12XE-Family uses 16-bit wide accesses without wait states for all peripherals and memories.

The non-multiplexed expanded bus interface available on the 144/208-Pin versions allows an easy

interface to external memories.

In addition to the I/O ports available in each module, up to 26 further I/O ports are available with interrupt

capability allowing Wake-Up from STOP or WAIT modes. The MC9S12XE-Family is available in 208-

Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options.

Features

• 16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

• INT (interrupt module)

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— Internal non-maskable high priority Memory Protection Unit interrupt

— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts

• EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)

— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces

— Each chip select output can be configured to complete transaction on either the time-out of one

of the two wait state generators or the deassertion of EWAIT signal

• MMC (module mapping control)

• DBG (debug module)

— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

• BDM (background debug mode)

• MPU (memory protection unit)

— 8 address regions definable per active program task

— Address range granularity as low as 8-bytes

— No write / No execute Protection Attributes

— Non-maskable interrupt on access violation

• XGATE

— Programmable, high performance I/O coprocessor module

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Performs logical, shifts, arithmetic, and bit operations on data

— Can interrupt the HCS12X CPU signalling transfer completion

— Triggers from any hardware module as well as from the CPU possible

— Two interrupt levels to service high priority tasks

— Hardware support for stack pointer initialisation

• OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

• IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

— No external components required

— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

• CRG (clock and reset generation)

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake up from STOP in self clock mode

• Memory Options

— 128K, 256k, 384K, 512K, 768K and 1M byte Flash

— 2K, 4K byte emulated EEPROM

— 12K, 16K, 24K, 32K, 48K and 64K Byte RAM

• Flash General Features

— 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

— Erase sector size 1024 bytes

— Automated program and erase algorithm

• D-Flash Features

— Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access.

— Dedicated commands to control access to the D-Flash memory over EEE operation.

— Single bit fault correction and double bit fault detection within a word during read operations.

— Automated program and erase algorithm with verify and generation of ECC parity bits.

— Fast sector erase and word program operation.

— Ability to program up to four words in a burst sequence

• Emulated EEPROM Features

— Automatic EEE file handling using an internal Memory Controller.

— Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset.

— Ability to monitor the number of outstanding EEE related buffer RAM words left to be

programmed into D-Flash memory.

— Ability to disable EEE operation and allow priority access to the D-Flash memory.

— Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory.

• Two 16-channel, 12-bit Analog-to-Digital Converters

— 8/10/12 Bit resolution

— 3µs, 10-bit single conversion time

— Left/right, signed/unsigned result data

— External and internal conversion trigger capability

— Internal oscillator for conversion in Stop modes

— Wake from low power modes on analog comparison > or <= match

• Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules)

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 16-bit modulus down counter with 8-bit precision prescaler

— Four 8-bit or two 16-bit pulse accumulators

• TIM (standard timer module)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 1 x 16-bit pulse accumulator

• PIT (periodic interrupt timer)

— Up to eight timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

— Time-out interrupt and peripheral triggers

• 8 PWM (pulse-width modulator) channels

— 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator

— programmable period and duty cycle per channel

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Three Serial Peripheral Interface Modules (SPI)

— Configurable for 8 or 16-bit data size

• Eight Serial Communication Interfaces (SCI)

— Standard mark/space non-return-to-zero (NRZ) format

— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• Two Inter-IC bus (IIC) Modules

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

— Broadcast mode support

— 10-bit address support

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3V and 5V range operation

— Low-voltage reset (LVR)

• Low-power wake-up timer (API)

— Available in all modes including Full Stop Mode

— Trimmable to +-5% accuracy

— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution

• Input/Output

— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins

— Hysteresis and configurable pull up/pull down device on all input pins

— Configurable drive strength on all output pins

• Package Options

— 208-pin MAPBGA

— 144-pin low-profile quad flat-pack (LQFP)

— 112-pin low-profile quad flat-pack (LQFP)

— 80-pin quad flat-pack (QFP)

• 50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency

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HCS12X HCS12X Microcontroller IC 16-Bit 50MHz 256KB (256K x 8) FLASH 112-LQFP (20x20)

Introduction

The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including

new features for enhanced system integrity and greater functionality. These new features include a

Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with

enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency

modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product

range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship

MC9S12XE100.

The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit

MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently

enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of

compatibility between the S12XE and S12XD families.

The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor

which is programmable in “C” language and runs at twice the bus frequency of the S12X with an

instruction set optimized for data movement, logic and bit manipulation instructions and which can service

any peripheral module on the device. The new enhanced version has improved interrupt handling

capability and is fully compatible with the existing XGATE module.

The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM,

eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-

channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an 8-

channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12),

two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit

standard timer module (TIM).

The MC9S12XE-Family uses 16-bit wide accesses without wait states for all peripherals and memories.

The non-multiplexed expanded bus interface available on the 144/208-Pin versions allows an easy

interface to external memories.

In addition to the I/O ports available in each module, up to 26 further I/O ports are available with interrupt

capability allowing Wake-Up from STOP or WAIT modes. The MC9S12XE-Family is available in 208-

Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options.

Features

• 16-Bit CPU12X

— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions

(MEM, WAV, WAVR, REV, REVW) which have been removed

— Enhanced indexed addressing

— Access to large data segments independent of PPAGE

• INT (interrupt module)

— Eight levels of nested interrupts

— Flexible assignment of interrupt sources to each interrupt level.

— External non-maskable high priority interrupt (XIRQ)

— Internal non-maskable high priority Memory Protection Unit interrupt

— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts

• EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)

— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces

— Each chip select output can be configured to complete transaction on either the time-out of one

of the two wait state generators or the deassertion of EWAIT signal

• MMC (module mapping control)

• DBG (debug module)

— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests

— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information

• BDM (background debug mode)

• MPU (memory protection unit)

— 8 address regions definable per active program task

— Address range granularity as low as 8-bytes

— No write / No execute Protection Attributes

— Non-maskable interrupt on access violation

• XGATE

— Programmable, high performance I/O coprocessor module

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Performs logical, shifts, arithmetic, and bit operations on data

— Can interrupt the HCS12X CPU signalling transfer completion

— Triggers from any hardware module as well as from the CPU possible

— Two interrupt levels to service high priority tasks

— Hardware support for stack pointer initialisation

• OSC_LCP (oscillator)

— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal

— Good noise immunity

— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal

— Transconductance sized for optimum start-up margin for typical crystals

• IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)

— No external components required

— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

• CRG (clock and reset generation)

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake up from STOP in self clock mode

• Memory Options

— 128K, 256k, 384K, 512K, 768K and 1M byte Flash

— 2K, 4K byte emulated EEPROM

— 12K, 16K, 24K, 32K, 48K and 64K Byte RAM

• Flash General Features

— 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure

correction and double fault detection

— Erase sector size 1024 bytes

— Automated program and erase algorithm

• D-Flash Features

— Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access.

— Dedicated commands to control access to the D-Flash memory over EEE operation.

— Single bit fault correction and double bit fault detection within a word during read operations.

— Automated program and erase algorithm with verify and generation of ECC parity bits.

— Fast sector erase and word program operation.

— Ability to program up to four words in a burst sequence

• Emulated EEPROM Features

— Automatic EEE file handling using an internal Memory Controller.

— Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset.

— Ability to monitor the number of outstanding EEE related buffer RAM words left to be

programmed into D-Flash memory.

— Ability to disable EEE operation and allow priority access to the D-Flash memory.

— Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory.

• Two 16-channel, 12-bit Analog-to-Digital Converters

— 8/10/12 Bit resolution

— 3µs, 10-bit single conversion time

— Left/right, signed/unsigned result data

— External and internal conversion trigger capability

— Internal oscillator for conversion in Stop modes

— Wake from low power modes on analog comparison > or <= match

• Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules)

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 16-bit modulus down counter with 8-bit precision prescaler

— Four 8-bit or two 16-bit pulse accumulators

• TIM (standard timer module)

— 8 x 16-bit channels for input capture or output compare

— 16-bit free-running counter with 8-bit precision prescaler

— 1 x 16-bit pulse accumulator

• PIT (periodic interrupt timer)

— Up to eight timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

— Time-out interrupt and peripheral triggers

• 8 PWM (pulse-width modulator) channels

— 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator

— programmable period and duty cycle per channel

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Three Serial Peripheral Interface Modules (SPI)

— Configurable for 8 or 16-bit data size

• Eight Serial Communication Interfaces (SCI)

— Standard mark/space non-return-to-zero (NRZ) format

— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• Two Inter-IC bus (IIC) Modules

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

— Broadcast mode support

— 10-bit address support

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3V and 5V range operation

— Low-voltage reset (LVR)

• Low-power wake-up timer (API)

— Available in all modes including Full Stop Mode

— Trimmable to +-5% accuracy

— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution

• Input/Output

— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins

— Hysteresis and configurable pull up/pull down device on all input pins

— Configurable drive strength on all output pins

• Package Options

— 208-pin MAPBGA

— 144-pin low-profile quad flat-pack (LQFP)

— 112-pin low-profile quad flat-pack (LQFP)

— 80-pin quad flat-pack (QFP)

• 50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency

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HCS12X HCS12X Microcontroller IC 16-Bit 80MHz 512KB (512K x 8) FLASH 144-LQFP (20x20)

MC9S12XDP512

Covers

S12XD, S12XB & S12XA Families

Introduction

The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency

advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family.

Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of

a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.

The MC9S12XD family introduces the performance boosting XGATE module. Using enhanced DMA

functionality, this parallel processing module offloads the CPU by providing high-speed data processing

and transfer between peripheral modules, RAM, Flash EEPROM and I/O ports. Providing up to 80 MIPS

of performance additional to the CPU, the XGATE can access all peripherals, Flash EEPROM and the

RAM block.

The MC9S12XD family is composed of standard on-chip peripherals including up to 512 Kbytes of Flash

EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces

(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,

10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel

pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two

inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XD family has full 16-bit data paths

throughout.

The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to

external memories

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit

operational requirements. System power consumption can be further improved with the new “fast exit from

stop mode” feature.

In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt

capability allowing wake-up from stop or wait mode.

Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP

or 80-pin QFP package without external bus interface. See Appendix E Derivative Differencesfor package

options.

MC9S12XD/B/A Family Features

• HCS12X Core

— 16-bit HCS12X CPU

– Upward compatible with MC9S12 instruction set

– Interrupt stacking and programmer’s model identical to MC9S12

– Instruction queue

– Enhanced indexed addressing

– Enhanced instruction set

— EBI (external bus interface)

— MMC (module mapping control)

— INT (interrupt controller)

— DBG (debug module to monitor HCS12X CPU and XGATE bus activity)

— BDM (background debug mode)

• XGATE (peripheral coprocessor)

— Parallel processing module off loads the CPU by providing high-speed data processing and

transfer

— Data transfer between Flash EEPROM, RAM, peripheral modules, and I/O ports

• PIT (periodic interrupt timer)

— Four timers with independent time-out periods

— Time-out periods selectable between 1 and 224 bus clock cycles

• CRG (clock and reset generator)

— Low noise/low power Pierce oscillator

— PLL

— COP watchdog

— Real time interrupt

— Clock monitor

— Fast wake-up from stop mode

• Port H & Port J with interrupt functionality

— Digital filtering

— Programmable rising or falling edge trigger

• Memory

— 512, 256 and 128-Kbyte Flash EEPROM

— 4 and 2-Kbyte EEPROM

— 32, 16 and 12-Kbyte RAM

• One 16-channel and one 8-channel ADC (analog-to-digital converter)

— 10-bit resolution

— External and internal conversion trigger capabilityFiveFourTwo 1M bit per second,

CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self-test operation

• ECT (enhanced capture timer)

— 16-bit main counter with 7-bit prescaler

— 8 programmable input capture or output compare channels

— Four 8-bit or two 16-bit pulse accumulators

• 8 PWM (pulse-width modulator) channels

— Programmable period and duty cycle

— 8-bit 8-channel or 16-bit 4-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces

— SixFourTwo asynchronous serial communication interfaces (SCI) with additional LIN support

and selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width

— ThreeTwo Synchronous Serial Peripheral Interfaces (SPI)

• TwoOne IIC (Inter-IC bus) Modules

— Compatible with IIC bus standard

— Multi-master operation

— Software programmable for one of 256 different serial clock frequencies

• On-Chip Voltage Regulator

— Two parallel, linear voltage regulators with bandgap reference

— Low-voltage detect (LVD) with low-voltage interrupt (LVI)

— Power-on reset (POR) circuit

— 3.3-V–5.5-V operation

— Low-voltage reset (LVR)

— Ultra low-power wake-up timer

• 144-pin LQFP, 112-pin LQFP, and 80-pin QFP packages

— I/O lines with 5-V input and drive capability

— Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation

— 5-V A/D converter inputs

— Operation at 80 MHz equivalent to 40-MHz bus speed

• Development support

— Single-wire background debug™ mode (BDM)

— Four on-chip hardware breakpoints

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S12Z S12 MagniV Microcontroller IC 16-Bit 32MHz 96KB (96K x 8) FLASH 48-LQFP (7x7)

Introduction

The MC9S12ZVC-Family is a new member of the S12 MagniV product line integrating a battery level

(12V) voltage regulator, supply voltage monitoring, high voltage inputs and a CAN physical interface. It's

primarily targeting at CAN nodes like sensors, switch panels or small actuators. It offers various

low-power modes and wakeup management to address state of the art power consumption requirements.

Some members of the MC9S12ZVC-Family are also offered for high temperature applications requiring

AEC-Q100 Grade 0 (-40℃ to +150C ambient operating temperature range).

The MC9S12ZVC-Family is based on the enhanced performance, linear address space S12Z core and

delivers an optimized solution with the integration of severalkey system components into a single device,

optimizing system architecture and achieving significant space savings.

Chip-Level Features

•On-chip modules available within the family include the following features:

•S12Z CPU core

•Up to 192 Kbyte on-chip flash with ECC

•Up to 2 Kbyte EEPROM with ECC

•Up to 12Kbyte on-chip SRAM with ECC

•Phase locked loop (IPLL) frequency multiplier with internal filter

•1 MHz internalRC oscillator with +/-1.3% accuracy over rated temperature range

•4-20MHz amplitude controlled pierce oscillator

•Internal COP (watchdog) module

•Analog-to-digital converter (ADC) with 12-bit resolution and up to 16 channels available on

external pins

•Two analog comparators (ACMP) with rail-to-rail inputs

•One 8-bit 5V digital-to-analog converter (DAC)

•Up to two serial peripheral interface (SPI) modules

•Up to two serial communication interface (SCI) modules

•SENT Transmitter Interface

•MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module

•One on-chip CAN physicallayer module

•8-channel timer module (TIM0) with input capture/output compare

•4-channel timer module (TIM1) with input capture/output compare (fast max 64MHz)

•Inter-IC (IIC) module

•4-channel 16-bit Pulse Width Modulation module (PWM0)

•4-channe1 16-bit Pulse Width Modulation module (PWM1) (fast max 64MHz)

•On-chip voltage regulator (VREG) for regulation of input supply and all interal voltages

•Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode

•Four pins to support 25 mA drive strength to VSSX

•One pin to support 20 mA drive strength from VDDX (EVDD)

•Two High Voltage Input (HVI) pins

•Supply Vsup monitoring with warning

•On-chip temperature sensor, temperature value can be measured with ADC or can generate a high

temperature interrupt