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IGLOO nano Field Programmable Gate Array (FPGA) IC 77 768 100-TQFP
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution,
small footprint packages, reprogrammability, and an abundance of advanced features.
The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-low power mode that
consumes nanoPower while retaining SRAM and register data. Flash*Freeze technology simplifies power management
through l/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO nano device is
completely functional in the system. This allows the IGLO0 nano device to control system power management based on
external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power.
Nonvolatile flash technology gives lGLOO nano devices the advantage of being a secure, low power, single-chip solution
that is Instant On. The IGLOO nano device is reprogrammable and offers time-to-market benefits at an ASIC-level unit
cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools.
IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning
circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and smaller devices have no PLL or RAM support.
IGLOO nano devices have up to 250 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71
user l/Os.
IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and packages for greater
customer value in high volume consumer, portable, and battery-backed markets. Features such as smaller footprint
packages designed with two-layer PCBs in mind, power consumption measured in nanoPower, Schmitt trigger, and bus
hold (hold previous l/O state in Flash*Freeze mode) functionality make these devices ideal for deployment in applications
that require high levels of flexibility and low cost.
Features and Benefits
Low Power
nanoPower Consumption-Industry's Lowest Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power Consumption while MaintainingFPGA Content
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
Small Footprint Packages
As Small as 3x3 mm in Size
Wide Range of Features
10,000 to 250,000 System Gates
Up to 36 kbits of True Dual-Port SRAM
Up to 71 User 1/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance
In-System Programming (ISP) and Security
ISP Using On-Chip 128-BitAdvanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant)
FlashLock®Designed to Secure FPGA Contents
1.2 V Programming
High-Performance Routing Hierarchy
Segmented,Hierarchical Routing and Clock Structure
Advanced I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V,and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages-up to 4 Banks per Chip
Single-Ended I/O Standards:LVTTL,LVCMOS 3.3V/2.5 V/ 1.8 V/1.5 V/1.2V
Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6V
Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575V
I/O Registers on Input, Output, and Enable Paths
Selectable Schmitt Trigger Inputs
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1(JTAG) Boundary Scan Test
Pin-Compatible Packages across the IGLOO®Family
Clock Conditioning Circuit(CCC) and PLLt
Up to Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations)
True Dual-Port SRAM(except x18 organization)
Enhanced Commercial Temperature Range
Tj=-20℃ to +85℃
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Shipment Date
2025/04/04 PM
Delivery Date
5-10 business days
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