A Comprehensive Guide To GAL22CV10-15LNC LOW VOLTAGE E2CMOS PLD GENERIC A

LOW VOLTAGE E2CMOS PLD GENERIC A

General Description

The NSC E²CMOS™ GAL人® devices combine a high per-formance CMOS process with electrically erasable floating

gate technology. This programmable memory technology applied to array logic provides designers with reconfigurable

logic and bipolar performance at significantly reduced pow-er levels.

The 24-pin GAL22V10 features 22 inputs, and 10 program-mable Output Logic Macro Cells (OLMCs) allowing each

TRI-STATE® output to be configured by the user. The archi-tecture of each output is user-programmable for registered

or combinatorial operation, active high or low polarity, and as an input, output or bidirectional I/O. This architecture

features variable product term distribution, from 8 to 16 logi-cal product terms to each output, as shown in the logic dia-

gram. CMOS circuitry allows the GAL22V10 to consume just 90 mA typical lcc which represents a 50% saving in power

when compared to its bipolar counterparts. Synchronous preset and asynchronous reset product terms have been

added which are common to all output registers to enhance system operation. The GAL22V10 is directly compatible

with the bipolar PAL22V10 in terms of functionality, fuse map, pinout, and electrical characteristics.

Programming is accomplished using industry standard avail-able hardware and software tools. NSC guarantees a mini-

mum 100 erase/write cycles.

Unique test circuitry and reprogrammable cells allow com-plete AC, DC, cell and functionality testing during manufac-

ture. Therefore, NSC guarantees 100% field programmabili-ty of all GAL devices. In addition, electronic signature is

available to provide positive device ID. A security circuit isbuilt-in, providing proprietary designs with copy protection.

Features

• High performance E²CMOS technology

     -15 ns maximum propagation delay

     -fmax = 45 MHz with feedback

     -TTL compatible 16 mA outputs

     -UltraMOS® Ill advanced CMOS technology

     -Internal pull-up resistor on all pins

• Electrically erasable cell technology

     -Reconfigurable logic

     -Reprogrammable cells

     -100% tested/guaranteed 100% yields

     -High speed electrical erasure(<50 ms)

     -20 year data retention

• Ten output logic macrocells

     -Maximum Flexibility

     -Programmable output polarity

     -Maximum flexibility for complex logic designs

     -Full function/fuse map/parametric compatibility with PAL22V10 devices

• Variable product term distribution

     -From 8 to 16 product terms per output data function

• Globai synchronous preset and asynchronous reset

• Preload and power-up reset of all registers

     -100% functional testability

• Fully supported by National OPAL™ and OPALjr development software

• Security cell prevents copying logic

How to choose FPGA for your project?