A Comprehensive Guide To GAL22CV10-LNC LOW VOLTAGE E2CMOS PLD GENERIC A

LOW VOLTAGE E2CMOS PLD GENERIC A

General Description

The EECMOS GAL22CV10 devices are fabricated using electricaly erasable floating gate technology. This program-

mable memory technology applied to array logic provides designers with reconfigurable logic and bipolar performance

at significantly reduced power levels.

The 24-pin GAL22CV10 features 10 programmable Output Logic Macrocells (OLMCs) allowing each TRI-STATE® out-

put to be configured by the user. The GAL22CV10 is also cabable of emulating most popular 24-pin PAL®devices.

Programming Is accomplished using popular hardware and software tools. NSC guarantees a minimum of 100 erase/

write cycles.

Unique test circurtry and reprogrammable cells allow com-plete AC, DC, cell, and functionality testing during manufac-

ture. Therefore, NSC guarantees 100% field programmabili-ty and functionality of NSC GAL® devices. In addition, a

securty circult is built-in, providing proprietary designs withcopy protection.

Features

• High performance EECMOS technology

     -10 ns maximum propagation delay

     -6 ns setup time delay

     -TTL compatible 16 mA outputs

     -2000V ESD protection

• Reduced power

     -lcc max =130 mA @ 25 MHz

• Electrically erasable cell technology

     -Reconfigurable logic

     -100% tested at manufacture

• Output Logic Macrocells (OLMCs)

     -Maximum flexibility for complex logic design

     -Programmable output polarity

     -Emulates popular PAL devices

• Fully supported by National OPALTM and OPALjr development software as well as 3rd-party PLD development tools

• Securty cell prevents copying logic

How to choose FPGA for your project?