A Comprehensive Guide To LCMXO2-2000ZE-1UWG49ITR1K MachXO2 Field Programmable Gate Array (FPGA) IC 40 75776 2112 49-UFBGA, WLCSP

MachXO2 Field Programmable Gate Array (FPGA) IC 40 75776 2112 49-UFBGA, WLCSP

General Description

The MachXO2 family of ultra-low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to

6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-engineered source

synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of

commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to

be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO2 devices are available in three options – ultra low power (ZE) and high performance (HC and HE) devices.

The ultra-low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Similarly, the

high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC devices have an

internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V. ZE and HE devices only

accept 1.2V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices

(ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same package. 

How to choose FPGA for your project?

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