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XP2 Field Programmable Gate Array (FPGA) IC 146 169984 5000 208-BFQFP
General Description
LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture
referred to as flexiFLASH.
The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK
embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with
TransFR, 128-bit AES Encryption and Dual-boot technologies.
The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in
mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs),
pre-engineered source synchronous I/O support and enhanced sysDSP blocks.
Lattice Diamond® design software allows large and complex designs to be efficiently implemented using the LatticeXP2
family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The Diamond
software uses the synthesis tool output along with the constraints from its floor planning tools to place and route the
design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and back-annotates it into the
design for timing verification.
Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By using
these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their
productivity.
Features
flexiFLASH™ Architecture
Instant-on
Infinitely reconfigurable
Single chip
FlashBAK™ technology
Serial TAG memory
Design security
Live Update Technology
TransFR™ technology
Secure updates with 128 bit AES encryption
Dual-boot with external SPI
sysDSP™ Block
Three to eight blocks for high performance Multiply and Accumulate
12 to 32 18x18 multipliers
Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers
Embedded and Distributed Memory
Up to 885 Kbits sysMEM™ EBR
Up to 83 Kbits Distributed RAM
sysCLOCK™ PLLs
Up to four analog PLLs per device
Clock multiply, divide and phase shifting
Flexible I/O Buffer
sysIO™ buffer supports:
– LVCMOS 33/25/18/15/12; LVTTL
– SSTL 33/25/18 class I, II
– HSTL15 class I; HSTL18 class I, II
– PCI
– LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
Pre-engineered Source SynchronousInterfaces
DDR / DDR2 interfaces up to 200 MHz
7:1 LVDS interfaces support display applications
XGMII
Density And Package Options
5k to 40k LUT4s, 86 to 540 I/Os
csBGA, TQFP, PQFP, ftBGA and fpBGA packages
Density migration supported
Flexible Device Configuration
SPI (master and slave) Boot Flash Interface
Dual Boot Image supported
Soft Error Detect (SED) macro embedded
System Level Support
IEEE 1149.1 and IEEE 1532 Compliant
On-chip oscillator for initialization & general use
Devices operate with 1.2V power supply
How to choose FPGA for your project?
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Shipment Date
2025/04/01 AM
Delivery Date
5-10 business days
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Sub-Total | $28.45 |
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