A Comprehensive Guide to TI60F100S3F2C4L FPGA TITAN 61HSIO 3PLL LP 100BGA

Titanium™ Field Programmable Gate Array (FPGA) IC 61 2726298 62016 100-BGA

Introduction

The Titanium Ti60 FPGA features the high-density, low-power Efinix® Quantum™ compute

fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60

FPGAs are designed for highly integrated mobile and edge devices that need low power, a

small footprint, and a multitude of I/Os. With ultra-low power Ti60 FPGAs, designers can

build products that are always on, providing enhanced capabilities for applications such as

mobile, edge, AI IoT, and sensor fusion.

Features

• High-density, low-power Quantum™ compute fabric

• Built on TSMC 16 nm process

• 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM

• High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting

• Versatile on-chip clocking

— Low-skew global network supporting 32 clock or control signals

— Regional and local clock networks

— PLL support

• FPGA interface blocks

— High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V)

— High-speed I/O (HSIO), configurable as:

– LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps

– MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to 1.5 Gbps

– Single-ended and differential I/O

— PLL

— Oscillator

• Flexible device configuration

— Standard SPI interface (active, passive, and daisy chain(1))

— JTAG interface

— Supports internal reconfiguration

• Single-event upset (SEU) detection feature

• Fully supported by the Efinity® software, an RTL-to-bitstream compiler

• Optional security feature

— Asymmetric bitstream authentication using RSA-4096

— Bitstream encryption/decryption using AES-GCM

How to choose FPGA for your project?

PDF