FIRST ORDER
FREE 10% DISCOUNT
Efinix, Inc.
Alarms, Buzzers, and Sirens
-
Stacked
Scrolling
|
Img
|
Pdf
|
Part Number
|
Manufacturers
|
Desc
|
In Stock
|
Packing
|
Rfq
|
||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 73 1069548 19728 169-VFBGA
|
9
|
169-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 278 4152320 84096 576-VFBGA
|
7250
|
576-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 130 2831360 54195 324-VFBGA
|
3
|
324-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 230 1510400 31680 400-BGA
|
5
|
400-BGA
|
|
||||||||||||||||||||||||
|
|
Titanium™ Field Programmable Gate Array (FPGA) IC 34 2726298 62016 64-BGA, WLCSP
|
3
|
64-BGA, WLCSP
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 195 1069548 19728 256-TFBGA Description The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
13
|
256-TFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 97 1044 19728 144-LQFP Introduction The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler |
1
|
144-LQFP
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 230 1069548 19728 400-BGA Introduction The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
3
|
400-BGA
|
|
||||||||||||||||||||||||
|
|
|
Titanium™ Field Programmable Gate Array (FPGA) IC 163 2726298 62016 225-BGA Introduction The Titanium Ti60 FPGA features the high-density, low-power Efinix® Quantum™ compute fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs are designed for highly integrated mobile and edge devices that need low power, a small footprint, and a multitude of I/Os. With ultra-low power Ti60 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as mobile, edge, AI IoT, and sensor fusion. Features • High-density, low-power Quantum™ compute fabric • Built on TSMC 16 nm process • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting • Versatile on-chip clocking — Low-skew global network supporting 32 clock or control signals — Regional and local clock networks — PLL support • FPGA interface blocks — High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V) — High-speed I/O (HSIO), configurable as: – LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps – MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to 1.5 Gbps – Single-ended and differential I/O — PLL — Oscillator • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain(1)) — JTAG interface — Supports internal reconfiguration • Single-event upset (SEU) detection feature • Fully supported by the Efinity® software, an RTL-to-bitstream compiler • Optional security feature — Asymmetric bitstream authentication using RSA-4096 — Bitstream encryption/decryption using AES-GCM How to choose FPGA for your project?
|
2
|
225-BGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 130 4152320 84096 324-VFBGA Introduction The T85 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T85 FPGAs supports a variety of applications that need wide I/O connectivity. The T85 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T85 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 52 TX pairs and 52 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, DDR3L, LPDDR3, LPDDR2 x32 PHY (supporting x16 or x32 DQ widths) with memory controller hard IP, up to 1066 Mbps • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals orPLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
7618
|
324-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 195 1069548 19728 256-TFBGA
|
28
|
256-TFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 256 2831360 54195 484-LFBGA
|
2
|
484-LFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 256 5536768 112128 484-LFBGA
|
2
|
484-LFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 130 1510400 31680 324-VFBGA
|
8
|
324-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Titanium™ Field Programmable Gate Array (FPGA) IC 163 2726298 62016 225-BGA
|
6574
|
225-BGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 97 1044 19728 144-LQFP Description The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
41
|
144-LQFP
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 130 1069548 19728 324-VFBGA Introduction The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
17
|
324-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 278 5536768 112128 576-VFBGA Introduction The T120 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T120 FPGAs supports a variety of applications that need wide I/O connectivity. The T120 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T120 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 52 TX pairs and 52 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, DDR3L, LPDDR3, LPDDR2 x32 PHY (supporting x16 or x32 DQ widths) with memory controller hard IP, 25.6 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
1
|
576-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Titanium™ Field Programmable Gate Array (FPGA) IC 34 2726298 62016 64-BGA, WLCSP Introduction The Titanium Ti60 FPGA features the high-density, low-power Efinix® Quantum™ compute fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs are designed for highly integrated mobile and edge devices that need low power, a small footprint, and a multitude of I/Os. With ultra-low power Ti60 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as mobile, edge, AI IoT, and sensor fusion. Features • High-density, low-power Quantum™ compute fabric • Built on TSMC 16 nm process • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting • Versatile on-chip clocking — Low-skew global network supporting 32 clock or control signals — Regional and local clock networks — PLL support • FPGA interface blocks — High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V) — High-speed I/O (HSIO), configurable as: – LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps – MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to 1.5 Gbps – Single-ended and differential I/O — PLL — Oscillator • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain(1)) — JTAG interface — Supports internal reconfiguration • Single-event upset (SEU) detection feature • Fully supported by the Efinity® software, an RTL-to-bitstream compiler • Optional security feature — Asymmetric bitstream authentication using RSA-4096 — Bitstream encryption/decryption using AES-GCM How to choose FPGA for your project?
|
3
|
64-BGA, WLCSP
|
|
||||||||||||||||||||||||
|
|
|
Titanium™ Field Programmable Gate Array (FPGA) IC 163 2726298 62016 225-BGA Introduction The Titanium Ti60 FPGA features the high-density, low-power Efinix® Quantum™ compute fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs are designed for highly integrated mobile and edge devices that need low power, a small footprint, and a multitude of I/Os. With ultra-low power Ti60 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as mobile, edge, AI IoT, and sensor fusion. Features • High-density, low-power Quantum™ compute fabric • Built on TSMC 16 nm process • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting • Versatile on-chip clocking — Low-skew global network supporting 32 clock or control signals — Regional and local clock networks — PLL support • FPGA interface blocks — High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V) — High-speed I/O (HSIO), configurable as: – LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps – MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to 1.5 Gbps – Single-ended and differential I/O — PLL — Oscillator • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain(1)) — JTAG interface — Supports internal reconfiguration • Single-event upset (SEU) detection feature • Fully supported by the Efinity® software, an RTL-to-bitstream compiler • Optional security feature — Asymmetric bitstream authentication using RSA-4096 — Bitstream encryption/decryption using AES-GCM How to choose FPGA for your project?
|
2849
|
225-BGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 195 1069548 19728 256-TFBGA
|
13
|
256-TFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 97 125952 7384 144-LQFP
|
25
|
144-LQFP
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 33 125952 7384 49-VFBGA
|
14
|
49-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 130 1510400 31680 324-VFBGA
|
1294
|
324-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Titanium™ Field Programmable Gate Array (FPGA) IC 163 2726298 62016 225-BGA
|
9065
|
225-BGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 195 1069548 19728 256-TFBGA Description The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
28
|
256-TFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 73 1069548 19728 169-VFBGA Introduction The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
7
|
169-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 33 78848 3888 49-VFBGA Introduction The T4 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface in a small footprint package for easy integration. T4 FPGAs support mobile, consumer, and IoT edge markets that need low power, low cost, and a small form factor. With ultra-low power T4 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, and power management. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Less than 150 μA typical core leakage current at 1.1 V • Ultra-small footprint package options • FPGA interface blocks — GPIO — PLL — Oscillator • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
3
|
49-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Trion® Field Programmable Gate Array (FPGA) IC 33 78848 3888 49-VFBGA Introduction The T4 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface in a small footprint package for easy integration. T4 FPGAs support mobile, consumer, and IoT edge markets that need low power, low cost, and a small form factor. With ultra-low power T4 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, and power management. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Less than 150 μA typical core leakage current at 1.1 V • Ultra-small footprint package options • FPGA interface blocks — GPIO — PLL — Oscillator • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
|
1137
|
49-VFBGA
|
|
||||||||||||||||||||||||
|
|
|
Titanium™ Field Programmable Gate Array (FPGA) IC 163 2726298 62016 225-BGA Introduction The Titanium Ti60 FPGA features the high-density, low-power Efinix® Quantum™ compute fabric wrapped with an I/O interface in a small footprint package for easy integration. Ti60 FPGAs are designed for highly integrated mobile and edge devices that need low power, a small footprint, and a multitude of I/Os. With ultra-low power Ti60 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as mobile, edge, AI IoT, and sensor fusion. Features • High-density, low-power Quantum™ compute fabric • Built on TSMC 16 nm process • 10-kbit high-speed, embedded SRAM, configurable as single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM • High-performance DSP blocks for multiplication, addition, subtraction, accumulation, and up to 15-bit variable-right-shifting • Versatile on-chip clocking — Low-skew global network supporting 32 clock or control signals — Regional and local clock networks — PLL support • FPGA interface blocks — High-voltage I/O (HVIO) (1.8, 2.5, 3.3 V) — High-speed I/O (HSIO), configurable as: – LVDS, subLVDS, Mini-LVDS, and RSDS (RX, TX, and bidirectional), up to 1.5 Gbps – MIPI lane I/O (DSI and CSI) in high-speed (HS) low-power (LP) modes, up to 1.5 Gbps – Single-ended and differential I/O — PLL — Oscillator • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain(1)) — JTAG interface — Supports internal reconfiguration • Single-event upset (SEU) detection feature • Fully supported by the Efinity® software, an RTL-to-bitstream compiler • Optional security feature — Asymmetric bitstream authentication using RSA-4096 — Bitstream encryption/decryption using AES-GCM How to choose FPGA for your project?
|
9065
|
225-BGA
|
|
||||||||||||||||||||||||
