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Trion® Field Programmable Gate Array (FPGA) IC 73 744489 12828 169-VFBGA
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15
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169-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 130 4152320 84096 324-VFBGA
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7618
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324-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 278 2831360 54195 576-VFBGA
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840
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576-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 130 1069548 19728 324-VFBGA
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8445
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324-VFBGA
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Titanium™ Field Programmable Gate Array (FPGA) IC 61 2726298 62016 100-BGA
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4
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100-BGA
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Trion® Field Programmable Gate Array (FPGA) IC 195 1069548 19728 256-TFBGA Description The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Low core leakage current (6.7 mA typical) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project? |
26
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256-TFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 33 125952 7384 49-VFBGA Introduction The T8 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface in a small footprint package for easy integration. T8 FPGAs support mobile, consumer, and IoT edge markets that need low power, low cost, and a small form factor. With ultra-low power T8 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, and power management. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Less than 150 μA typical core leakage current at 1.1 V(1) • Ultra-small footprint package options • FPGA interface blocks — GPIO — PLL — LVDS 600 Mbps per lane with up to 6 TX pairs and 6 RX pairs(2) — Oscillator • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces(3) • Flexible on-chip clocking — 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler |
3
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49-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 33 1070080 19728 80-BGA, WLCSP Introduction The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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15
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80-BGA, WLCSP
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Trion® Field Programmable Gate Array (FPGA) IC 33 125952 7384 49-VFBGA Introduction The T8 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface in a small footprint package for easy integration. T8 FPGAs support mobile, consumer, and IoT edge markets that need low power, low cost, and a small form factor. With ultra-low power T8 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, and power management. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Less than 150 μA typical core leakage current at 1.1 V(1) • Ultra-small footprint package options • FPGA interface blocks — GPIO — PLL — LVDS 600 Mbps per lane with up to 6 TX pairs and 6 RX pairs(2) — Oscillator • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces(3) • Flexible on-chip clocking — 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler |
14
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49-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 230 1069548 19728 400-BGA Introduction The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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6259
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400-BGA
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Trion® Field Programmable Gate Array (FPGA) IC 195 1069548 19728 256-TFBGA
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26
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256-TFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 256 4152320 84096 484-LFBGA
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740
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484-LFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 33 78848 3888 49-VFBGA
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39
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49-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 230 1510400 31680 400-BGA
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4
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400-BGA
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Titanium™ Field Programmable Gate Array (FPGA) IC 61 2726298 62016 100-BGA
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3
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100-BGA
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Trion® Field Programmable Gate Array (FPGA) IC 195 744489 12828 256-TFBGA Description The T13 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T13 FPGAs supports a variety of applications that need wide I/O connectivity. The T13 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 13 TX pairs and 13 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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15
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256-TFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 73 744489 12828 169-VFBGA Introduction The T13 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T13 FPGAs supports a variety of applications that need wide I/O connectivity. The T13 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 13 TX pairs and 13 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler |
15
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169-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 55 125952 7384 81-VFBGA Introduction The T8 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface in a small footprint package for easy integration. T8 FPGAs support mobile, consumer, and IoT edge markets that need low power, low cost, and a small form factor. With ultra-low power T8 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, and power management. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Less than 150 μA typical core leakage current at 1.1 V(1) • Ultra-small footprint package options • FPGA interface blocks — GPIO — PLL — LVDS 600 Mbps per lane with up to 6 TX pairs and 6 RX pairs(2) — Oscillator • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces(3) • Flexible on-chip clocking — 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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9
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81-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 55 125952 7384 81-VFBGA Introduction The T8 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface in a small footprint package for easy integration. T8 FPGAs support mobile, consumer, and IoT edge markets that need low power, low cost, and a small form factor. With ultra-low power T8 FPGAs, designers can build products that are always on, providing enhanced capabilities for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, and power management. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Less than 150 μA typical core leakage current at 1.1 V(1) • Ultra-small footprint package options • FPGA interface blocks — GPIO — PLL — LVDS 600 Mbps per lane with up to 6 TX pairs and 6 RX pairs(2) — Oscillator • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces(3) • Flexible on-chip clocking — 12 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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13
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81-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 130 1510400 31680 324-VFBGA Introduction The T35 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T35 FPGAs supports a variety of applications that need wide I/O connectivity. The T35 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T35 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, DDR3L, LPDDR3, LPDDR2 x16 PHY (supporting x16 DQ widths) with memory controller hard IP, 25.6 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — Low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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1294
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324-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 195 744489 12828 256-TFBGA
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19
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256-TFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 130 5536768 112128 324-VFBGA
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5121
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324-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 130 125952 84096 324-VFBGA
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1
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324-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 130 1510400 31680 324-VFBGA
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11
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324-VFBGA
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Titanium™ Field Programmable Gate Array (FPGA) IC 61 2726298 62016 100-BGA
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6617
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100-BGA
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Trion® Field Programmable Gate Array (FPGA) IC 73 1069548 19728 169-VFBGA Description The T20 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T20 FPGAs supports a variety of applications that need wide I/O connectivity. The T20 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T20 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, LPDDR3, LPDDR2 x16 PHY with memory controller hard IP, 12.8 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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9
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169-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 73 744489 12828 169-VFBGA Introduction The T13 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T13 FPGAs supports a variety of applications that need wide I/O connectivity. The T13 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • Core leakage current as low as 6.8 mA(1) • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 13 TX pairs and 13 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface — Optional Mask Programmable Memory (MPM) capability • Fully supported by the Efinity® software, an RTL-to-bitstream compiler |
14
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169-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 130 1510400 31680 324-VFBGA Introduction The T35 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T35 FPGAs supports a variety of applications that need wide I/O connectivity. The T35 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T35 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, DDR3L, LPDDR3, LPDDR2 x16 PHY (supporting x16 DQ widths) with memory controller hard IP, 25.6 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — Low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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11
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324-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 278 4152320 84096 576-VFBGA Introduction The T85 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T85 FPGAs supports a variety of applications that need wide I/O connectivity. The T85 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T85 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 52 TX pairs and 52 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, DDR3L, LPDDR3, LPDDR2 x32 PHY (supporting x16 or x32 DQ widths) with memory controller hard IP, up to 1066 Mbps • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — 16 low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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839
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576-VFBGA
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Trion® Field Programmable Gate Array (FPGA) IC 230 1510400 31680 400-BGA Introduction The T35 FPGA features the high-density, low-power Efinix® Quantum™ architecture wrapped with an I/O interface for easy integration. With a high I/O to logic ratio and differential I/O support, T35 FPGAs supports a variety of applications that need wide I/O connectivity. The T35 also includes a MIPI D-PHY with a built-in, royalty-free CSI-2 controller, which is the most popular camera interface used in the mobile industry. Additionally, T35 FPGAs support a DDR3, LPDDR3, LPDDR2 PHY with memory controller hard IP that provides faster access to data stored in memory. The carefully tailored combination of core resources and I/O provides enhanced capability for applications such as embedded vision, voice and gesture recognition, intelligent sensor hubs, power management, and LED drivers. Features • High-density, low-power Quantum™ architecture • Built on SMIC 40 nm process • FPGA interface blocks — GPIO — PLL — LVDS 800 Mbps per lane with up to 20 TX pairs and 26 RX pairs — MIPI DPHY with CSI-2 controller hard IP, 1.5 Gbps per lane — DDR3, DDR3L, LPDDR3, LPDDR2 x16 PHY (supporting x16 DQ widths) with memory controller hard IP, 25.6 Gbps aggregate bandwidth • Programmable high-performance I/O — Supports 1.8, 2.5, and 3.3 V single-ended I/O standards and interfaces • Flexible on-chip clocking — Low-skew global clock signals can be driven from off-chip external clock signals or PLL synthesized clock signals — PLL support • Flexible device configuration — Standard SPI interface (active, passive, and daisy chain) — JTAG interface • Fully supported by the Efinity® software, an RTL-to-bitstream compiler How to choose FPGA for your project?
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9526
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400-BGA
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