Freescale Semiconductor

HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 32KB (32K x 8) FLASH 52-QFP (10x10)

Overview 

Device Introduction

The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general purpose industrial and automotive network applications. All MC9S12C-Family / MC9S12GC-Family members feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface

(SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC).

The MC9S12C128-Family members also feature a CAN 2.0 A, B software compatible module (MSCAN12).

All MC9S12C-Family / MC9S12GC-Family devices feature full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with wake-up capability from stop or wait mode. The devices are available in 48-, 52-, and 80-pin QFP packages, with the 80-pin version pin compatible to the HCS12 A, B, and D Family derivatives.

Device Features

• 16-bit HCS12 core:

— HCS12 CPU

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to M68HC11

– Instruction queue

– Enhanced indexed addressing

— MMC (memory map and interface)

— INT (interrupt control)

— BDM (background debug mode)

— DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)

— MEBI (multiplexed expansion bus interface) available only in 80-pin package version

• Wake-up interrupt inputs:

— Up to 12 port bits available for wake up interrupt function with digital filtering

• Memory options:

— 16K or 32Kbyte Flash EEPROM (erasable in 512-byte sectors)

64K, 96K, or 128Kbyte Flash EEPROM (erasable in 1024-byte sectors)

— 1K, 2K or 4K Byte RAM

• Analog-to-digital converters:

— One 8-channel module with 10-bit resolution

— External conversion trigger capability

• Available on MC9S12C Family:

— One 1M bit per second, CAN 2.0 A, B software compatible module

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit

— Four separate interrupt channels for Rx, Tx, error, and wake-up

— Low-pass filter wake-up function

— Loop-back for self test operation

• Timer module (TIM):

— 8-channel timer

— Each channel configurable as either input capture or output compare

— Simple PWM mode

— Modulo reset of timer counter

— 16-bit pulse accumulator

— External event counting

— Gated time accumulation

• PWM module:

— Programmable period and duty cycle

— 8-bit 6-channel or 16-bit 3-channel

— Separate control for each pulse width and duty cycle

— Center-aligned or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

— Fast emergency shutdown input

• Serial interfaces:

— One asynchronous serial communications interface (SCI)

— One synchronous serial peripheral interface (SPI)

• CRG (clock reset generator module)

— Windowed COP watchdog

— Real time interrupt

— Clock monitor

— Pierce or low current Colpitts oscillator

— Phase-locked loop clock frequency multiplier

— Limp home mode in absence of external clock

— Low power 0.5MHz to 16MHz crystal oscillator reference clock

• Operating frequency:

— 32MHz equivalent to 16MHz bus speed for single chip

— 32MHz equivalent to 16MHz bus speed in expanded bus modes

— Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed

— All 9S12GC Family members allow a 50MHz operating frequency.

• Internal 2.5V regulator:

— Supports an input voltage range from 2.97V to 5.5V

— Low power mode capability

— Includes low voltage reset (LVR) circuitry

— Includes low voltage interrupt (LVI) circuitry

• 48-pin LQFP, 52-pin LQFP, or 80-pin QFP package:

— Up to 58 I/O lines with 5V input and drive capability (80-pin package)

— Up to 2 dedicated 5V input only lines (IRQ, XIRQ)

— 5V 8 A/D converter inputs and 5V I/O

• Development support:

— Single-wire background debug™ mode (BDM)

— On-chip hardware breakpoints

— Enhanced DBG12 debug features

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HCS12 HCS12 Microcontroller IC 16-Bit 25MHz 256KB (256K x 8) FLASH 80-QFP (14x14)

Product Brief

16-Bit Microcontroller

Designed for automotive multiplexing applications, members of the MC9S12D-Family of 16 bit Flashbased

microcontrollers are fully pin compatible and enable users to choose between different memory

and peripheral options for scalable designs. All MC9S12D-Family members are composed of standard

on-chip peripherals including a 16-bit central processing unit (CPU12), up to 512K bytes of Flash

EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications

interfaces (SCI), three serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two

8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM),

J1850 interface and up to five CAN 2.0 A, B software compatible modules (MSCAN12). System

resource mapping, clock generation, interrupt control and bus interfacing are managed by the system

integration module (SIM). The MC9S12D-Family has full 16-bit data paths throughout, however, the

external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for

lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be

adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22

I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode.

Features

• 16-bit CPU12

— Upward compatible with M68HC11 instruction set

— Interrupt stacking and programmer’s model identical to M68HC11

— HCS12 Instruction queue

— Enhanced indexed addressing

• Multiplexed bus

— Single chip or expanded

— 16 address/16 data wide or 16 address/8 data narrow modes

— External address space 1MByte for Data and Program space (112 pin package only)

• Wake-up interrupt inputs depending on the package option

— 8-bit port H

— 2-bit port J1:0

— 2-bit port J7:6 shared with IIC, CAN4 and CAN0 module

— 8-bit port P shared with PWM or SPI1,2

• Memory options

— 32K, 64K, 128K, 256K, 512K Byte Flash EEPROM

— 1K, 2K, 4K Byte EEPROM

— 2K, 4K, 8K, 12K, 14K Byte RAM

• Analog-to-Digital Converters

— One or two 8-channel modules with 10-bit resolution depending on the package option

— External conversion trigger capability

• Up to five 1M bit per second, CAN 2.0 A, B software compatible modules

— Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

— Four separate interrupt channels for Receive, Transmit, Error and Wake-up

— Low-pass filter wake-up function in STOP mode

— Loop-back for self test operation

• Enhanced Capture Timer (ECT)

— 16-bit main counter with 7-bit prescaler

— 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer

— Input capture filters and buffers, three successive captures on four channels, or two captures on four

channels with a capture/compare selectable on the remaining four

— Four 8-bit or two 16-bit pulse accumulators

— 16-bit modulus down-counter with 4-bit prescaler

— Four user-selectable delay counters for signal filtering

• 8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages)

— 8-bit, 8-channel or 16-bit, 4-channel

— Separate control for each pulse width and duty cycle

— Center- or left-aligned outputs

— Programmable clock select logic with a wide range of frequencies

• Serial interfaces

— Two asynchronous serial communications interfaces (SCI)

— Up to three synchronous serial peripheral interfaces (SPI)

— IIC

• SAE J1850 Compatible Module (BDLC)

— 10.4 kbps Variable Pulse Width format

— Byte level receive and transmit

— 4x receive mode supported

• SIM (System Integration Module)

— CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)

— MEBI (multiplexed external bus interface)

— INT (interrupt control)

• Clock generation

— Phase-locked loop clock frequency multiplier

— Limp home mode in absence of external clock

— Clock Monitor

— Low power 0.5 to 16 MHz crystal oscillator reference clock

• Operating frequency for ambient temperatures TA -40°C <= TA <= 125°C

— 50MHz equivalent to 25MHz Bus Speed for single chip

40MHz equivalent to 20MHz Bus Speed in expanded bus modes.

• Internal 5V to 2.5V Regulator

• 112-Pin LQFP or 80-Pin QFP package

— I/O lines with 5V input and drive capability

— 5V A/D converter inputs and 5V I/O

— 2.5V logic supply

• Development support

— Single-wire background debug™ mode (BDM)

— On-chip hardware breakpoints