Lattice Semiconductor Corporation

iCE40 UltraLite™ Field Programmable Gate Array (FPGA) IC 26 57344 1248 36-VFBGA

General Description

iCE40 UltraLite family is an optimum logic, smallest footprint, low I/O count ultra-low power FPGA and sensor manager

with instant on capability. It is designed for ultra-low power mobile applications, such as smartphones, tabletsand

hand-held devices. The iCE40 UltraLite family includes integrated blocks to interface with virtually all mobile sensors and

application processors. The iCE40 UltraLite family also features two on-chip oscillators, 10 kHz and 48 MHz. The LFOSC

(10 kHz) is ideal for low power function in always-on applications, while HFOSC (48 MHz) can beused for awaken activities.

The hardened RGB PWM IP, with the three 24 mA constant current RGB LED outputs on the iCE40 UltraLite provides all

the necessary logic to directly drive the service LED, without the need of external MOSFET or buffer.

The 400 mA constant current IR driver output provides a direct interface to external LED for application such as IrDA

functions. Users simply implement the hardened TX/RX pulse logic that meets their needs, and connect the IRdriver

directly to the LED, without the need of external MOSFET or buffer. The 100 mA Barcode Emulation driveroutput provides

a direct interface for applications such as barcode scanning. The 100 mA and 400 mA drivers canalso be combined to be

used as a 500 mA IR driver if higher than 400 mA current drive is required.

The iCE40 UltraLite family of devices are targeting for mobile applications to perform functions such as IrDA, Service LED,

Barcode Emulation, GPIO Expander, SDIO Level Shift, and other custom functions.

The iCE40 UltraLite family features two device densities of 640 or 1K Look Up Tables (LUTs) of logic with programmable

I/Os that can be used as an interface port or general purpose I/O. It also has up to 56 kbits of Block RAMs towork with

user logic. 

Features

• Flexible Logic Architecture

      Two devices with 640 or 1K LUTs

      Offered in 16-ball WLCSP package

      Offered in 36-ball ucBGA package

• Ultra-low Power Devices

      Advanced 40 nm ultra-low power process

      Typical 35 µA standby current which equals42 uW standby power consumption

• Embedded and Distributed Memory

      Up to 56 kbits sysMEM™ Embedded Block RAM

• Two Hardened Interfaces

      Two optional FIFO mode I2C interface up to1 MHz

      Either master or slave

• Two On-Chip Oscillators

      Low Frequency Oscillator - 10 kHz

      High Frequency Oscillator - 48 MHz

• Hardened PWM circuit for RGB

• Hardened TX/RX Pulse Logic circuit for IRLED

• 24 mA Current Drive RGB LED Outputs

      Three drive outputs in each device

      User selectable sink current up to 24 mA

• 400 or 500 mA Current Drive IR LED Output

      One IR drive output in each device

      User selectable sink current up to 400 mA

      Can be combined with 100 mA Barcode driver toform 500 mA IR driver

• 100 mA Current Drive Barcode Emulator

      One barcode driver output in each device

      User selectable sink current up to 100 mA

      Can be combined with 400 mA IR driver to useas 500 mA IR driver

• Flexible On-Chip Clocking

      Eight low skew global signal resource, six canbe directly driven from external pins

      One PLL with dynamic interface per device

• Flexible Device Configuration

      SRAM is configured through:

      — Standard SPI Interface

      — Internal Nonvolatile Configuration Memory(NVCM)

• Ultra-Small Form Factor

      As small as 1.409 mm x 1.409 mm

• Applications

      Smartphones

      Tablets and Consumer Handheld Devices

      Handheld Industrial Devices

      Multi Sensor Management Applications

      IR remote, Barcode emulator

      RGB light control

How to choose FPGA for your project?

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MachXO3 Field Programmable Gate Array (FPGA) IC 28 65536 1280 36-UFBGA, WLCSP

General Description

MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and

I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the

integrated support for latest industry standard I/O.

The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to

9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced

configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI

controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features

allow these devices to be used in low cost, high volume applications such as consumer electronics, compute and storage,

wireless communications, industrial control, and automotive systems.

The MachXO3L/LF devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the

fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V.

E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E

are functionally compatible with each other.

The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration within the same package.

Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters.

The MachXO3L/LF devices offer enhanced I/O features  such as drive strength control, slew rate control, PCI compatibility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a “per-pin” basis. A user-programmable internal oscillator is included in

MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in

functions such as LED control, keyboard scanner and similar state machines.

The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG

test access port or through the I²C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external

Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route

the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-annotate it into the

design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP

cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their

productivity.

Features

• Solutions

      Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

      Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications

      High I/O logic, lowest cost I/O, high I/O devices for I/O expansion applications

• Flexible Architecture

      Logic Density ranging from 64 to 9.4 k LUT4

      High I/O to LUT ratio with up to 384 I/O pins

• Advanced Packaging

      0.4 mm pitch: 1 k to 4 k densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm × 3.8 mm) with 28 to

      63 I/O

      0.5 mm pitch: 640 to 9.4 k LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to281 I/O

      0.8 mm pitch: 1 k to 9.4 k densities with up to 384 I/O in BGA packages

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/O

      Generic DDR, DDRx2, DDRx4

• High Performance, Flexible I/O Buffer

      Programmable sysI/O™ buffer supports wide range of interfaces:

            LVCMOS 3.3/2.5/1.8/1.5/1.2

            LVTTL

            LVDS, Bus-LVDS, MLVDS, LVPECL

            MIPI D-PHY Emulated

            Schmitt trigger inputs, up to 0.5 V hysteresis

      Ideal for I/O bridging applications

      I/O support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

            Wide input frequency range (7 MHz to 400 MHz).

• Non-volatile, Multi-time Programmable

      Instant-on

            Powers up in microseconds

      Optional dual boot with external SPI memory

      Single-chip, secure solution

      Programmable through JTAG, SPI or I2C

      MachXO3L includes multi-time programmable NVCM

      MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle for commercial/industrial devices and 10,000 for

      automotive devices

      Supports background programming of non volatile memory

• TransFR Reconfiguration

      In-field logic update while I/O holds the system state

• Enhanced System Level Support

      On-chip hardened functions: SPI, I2C, timer/counter

      On-chip oscillator with 5.5% accuracy for commercial/industrial devices

      Unique TraceID for system tracking

      Single power supply with extended operatingrange

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Applications

      Consumer Electronics

      Compute and Storage

      Wireless Communications

      Industrial Control Systems

      Automotive System

• Low Cost Migration Path

      Migration from the Flash based MachXO3LF to the NVCM based MachXO3L

      Pin compatible and equivalent timing

How to choose FPGA for your project?

PDF

MachXO3 Field Programmable Gate Array (FPGA) IC 100 94208 4320 121-VFBGA, CSPBGA

General Description

MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and

I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the

integrated support for latest industry standard I/O.

The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to

9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced

configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI

controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features

allow these devices to be used in low cost, high volume applications such as consumer electronics, compute and storage,

wireless communications, industrial control, and automotive systems.

The MachXO3L/LF devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the

fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V.

E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E

are functionally compatible with each other.

The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration within the same package.

Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters.

The MachXO3L/LF devices offer enhanced I/O features  such as drive strength control, slew rate control, PCI compatibility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a “per-pin” basis. A user-programmable internal oscillator is included in

MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in

functions such as LED control, keyboard scanner and similar state machines.

The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG

test access port or through the I²C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external

Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route

the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-annotate it into the

design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP

cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their

productivity.

Features

• Solutions

      Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

      Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications

      High I/O logic, lowest cost I/O, high I/O devices for I/O expansion applications

• Flexible Architecture

      Logic Density ranging from 64 to 9.4 k LUT4

      High I/O to LUT ratio with up to 384 I/O pins

• Advanced Packaging

      0.4 mm pitch: 1 k to 4 k densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm × 3.8 mm) with 28 to

      63 I/O

      0.5 mm pitch: 640 to 9.4 k LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to281 I/O

      0.8 mm pitch: 1 k to 9.4 k densities with up to 384 I/O in BGA packages

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/O

      Generic DDR, DDRx2, DDRx4

• High Performance, Flexible I/O Buffer

      Programmable sysI/O™ buffer supports wide range of interfaces:

            LVCMOS 3.3/2.5/1.8/1.5/1.2

            LVTTL

            LVDS, Bus-LVDS, MLVDS, LVPECL

            MIPI D-PHY Emulated

            Schmitt trigger inputs, up to 0.5 V hysteresis

      Ideal for I/O bridging applications

      I/O support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

            Wide input frequency range (7 MHz to 400 MHz).

• Non-volatile, Multi-time Programmable

      Instant-on

            Powers up in microseconds

      Optional dual boot with external SPI memory

      Single-chip, secure solution

      Programmable through JTAG, SPI or I2C

      MachXO3L includes multi-time programmable NVCM

      MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle for commercial/industrial devices and 10,000 for

      automotive devices

      Supports background programming of non volatile memory

• TransFR Reconfiguration

      In-field logic update while I/O holds the system state

• Enhanced System Level Support

      On-chip hardened functions: SPI, I2C, timer/counter

      On-chip oscillator with 5.5% accuracy for commercial/industrial devices

      Unique TraceID for system tracking

      Single power supply with extended operatingrange

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Applications

      Consumer Electronics

      Compute and Storage

      Wireless Communications

      Industrial Control Systems

      Automotive System

• Low Cost Migration Path

      Migration from the Flash based MachXO3LF to the NVCM based MachXO3L

      Pin compatible and equivalent timing

How to choose FPGA for your project?

PDF