Lattice Semiconductor Corporation

iCE40 UltraPlus™ Field Programmable Gate Array (FPGA) IC 39 1171456 5280 48-VFQFN Exposed Pad

General Description

iCE40 UltraPlus™ family from Lattice Semiconductor is an ultra-low power FPGA and sensor manager designed for

ultra-low power mobile applications, such as smartphones, tablets and hand-held devices. iCE40 UltraPlus is compatible

with Lattice's iCE40 Ultra family devices, containing all the functions iCE40 Ultra family has except the high current IR LED

driver. In addition, the iCE40 UltraPlus features an additional 1 Mb SRAM, additional DSP blocks, with additional LUTs, all

which can be used to support an always-on Voice Recognition function in the mobile devices, without the need to keep

the higher power consuming voice codec on allthe time.

The iCE40 UltraPlus family includes integrated SPI and I²C blocks to interface with virtually all mobile sensors and

application processors. In addition, the iCE40 UltraPlus family also features two I/O pins that can support the interface to

I3C devices. There are two on-chip oscillators, 10 kHz and 48 MHz, the LFOSC (10 kHz) is ideal for low power function in

always-onapplications, while HFOSC (48 MHz) can be used for awaken activities.

The iCE40 UltraPlus family also features DSP functional block to off-load Application Processor to pre-process information

sent from the mobile device, such as voice data. The RGB PWM IP, with the three 24 mA constant current RGB outputs on

the iCE40 UltraPlus provides all the necessary logic to directly drive the service LED, without the need of external MOSFET

or buffer.

The iCE40 UltraPlus family of devices are targeting for mobile applications to perform all the functions in iCE40 Ultra

devices, such as Service LED, GPIO Expander, SDIO Level Shift, and other custom functions. In addition, the iCE40

UltraPlus family devices are also targeting for Voice Recognition application.

The iCE40 UltraPlus family features two device densities, 2800 to 5280 Look Up Tables (LUTs) of logic with programmable

I/Os that can be used as either SPI/I²C interface ports or general purpose I/O’s. Two of the iCE40 UltraPlus I/Os can be

used to interface to higher performance I3C. It also has up to 120 kb of Block RAMs, plus 1024 kb of Single Port SRAMs

to work with user logic.

Features

• Flexible Logic Architecture

      Two devices with 2800 to 5280 LUTs

      Offered in WLCS and QFN packages

• Ultra-low Power Devices

      Advanced 40 nm low power process

      As low as 100 µA standby current typical

• Embedded Memory

      Up to 1024 kb Single Port SRAM

      Up to 120 kb sysMEM™ Embedded Block RAM

• Two Hardened I²C Interfaces

      Two I/O pins to support I3C interface

• Two Hardened SPI Interfaces

• Two On-Chip Oscillators

      Low Frequency Oscillator – 10 kHz

      High Frequency Oscillator – 48 MHz

• 24 mA Current Drive RGB LED Outputs

      Three drive outputs in each device

      User selectable sink current up to 24 mA

• On-chip DSP

      Signed and unsigned 8-bit or 16-bit functions

      Functions include Multiplier, Accumulator, and Multiply-Accumulate (MAC)

• Flexible On-Chip Clocking

      Eight low skew global signal resource, six can be directly driven from external pins

      One PLL with dynamic interface per device

• Flexible Device Configuration

      SRAM is configured through:

      Standard SPI Interface

      Internal Nonvolatile Configuration Memory (NVCM)

• Ultra-Small Form Factor

      As small as 2.11 mm × 2.54 mm

• Applications

      Always-On Voice Recognition Application

      Smartphones

      Tablets and Consumer Handheld Devices

      Handheld Commercial and Industrial Devices

      Multi Sensor Management Applications

      Sensor Pre-processing and Sensor Fusion

      Always-On Sensor Applications

      USB 3.1 Type C Cable Detect / Power Delivery Applications

MachXO2 Field Programmable Gate Array (FPGA) IC 21 65536 1280 32-UFQFN Exposed Pad

General Description

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to

6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source

synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of

commonly used functions such as SPI controller, I²C controller and timer/counter. These features allow these devices to

be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices.

The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the

high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an

internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only

accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices

(ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same

package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of

interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati bility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a“per-pin”basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be

divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state

machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices

can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test

access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash

memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2

family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the

synthesis tool output along with the user-specified preferences and constraints to place and route the design in the

MachXO2 device. These tools extract the timing from the routing and back-annotate it intothe design for timing

verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as

standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

Features

• Flexible Logic Architecture

      Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

• Ultra Low Power Devices

      Advanced 65 nm low power process

      As low as 22 µW standby power

      Programmable low swing differential I/Os

      Stand-by mode and other power saving options

• Embedded and Distributed Memory

      Up to 240 kbits sysMEM™ Embedded BlockRAM

      Up to 54 kbits Distributed RAM

      Dedicated FIFO control logic

• On-Chip User Flash Memory

      Up to 256 kbits of User Flash Memory

      100,000 write cycles

      Accessible through WISHBONE, SPI, I2C and JTAG interfaces

      Can be used as soft processor PROM or as Flash memory

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/Os

      Generic DDR, DDRX2, DDRX4

      Dedicated DDR/DDR2/LPDDR memory with DQS support

• High Performance, Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      – LVCMOS 3.3/2.5/1.8/1.5/1.2

      – LVTTL

      – PCI

      – LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

      – SSTL 25/18

      – HSTL 18

      – Schmitt trigger inputs, up to 0.5 V hysteresis

      I/Os support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

      – Wide input frequency range (7 MHz to 400 MHz)

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single-chip, secure solution

      Programmable through JTAG, SPI or I²C

      Supports background programming of non-vola-tile memory

      Optional dual boot with external SPI memory

• TransFR™ Reconfiguration

      In-field logic update while system operates

• Enhanced System Level Support

      On-chip hardened functions: SPI, I²C, timer/counter

      On-chip oscillator with 5.5% accuracy

      Unique TraceID for system tracking

      One Time Programmable (OTP) mode

      Single power supply with extended operating range

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Broad Range of Package Options

      TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN package options

      Small footprint package options

      – As small as 2.5 mm x 2.5 mm

      Density migration supported

      Advanced halogen-free packaging

How to choose FPGA for your project?

PDF

MachXO3 Field Programmable Gate Array (FPGA) IC 206 65536 1280 256-LFBGA

General Description

MachXO3™ device family is an Ultra-Low Density family that supports the most advanced programmable bridging and

I/O expansion. It has the breakthrough I/O density and the lowest cost per I/O. The device I/O features have the

integrated support for latest industry standard I/O.

The MachXO3L/LF family of low power, instant-on, non-volatile PLDs has five devices with densities ranging from 640 to

9400 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded

Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced

configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI

controller, I2C controller and timer/counter. MachXO3LF devices also support User Flash Memory (UFM). These features

allow these devices to be used in low cost, high volume applications such as consumer electronics, compute and storage,

wireless communications, industrial control, and automotive systems.

The MachXO3L/LF devices are designed on a 65 nm non-volatile low power process. The device architecture has several

features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and

oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power

for all members of the family.

The MachXO3L/LF devices are available in two versions C and E with two speed grades: -5 and -6, with -6 being the

fastest. C devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V.

E devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply voltage both C and E

are functionally compatible with each other.

The MachXO3L/LF PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving

2.5 x 2.5 mm WLCSP to the 19 x 19 mm caBGA. MachXO3L/LF devices support density migration within the same package.

Table 1.1 shows the LUT densities, package and I/O options, along with other key parameters.

The MachXO3L/LF devices offer enhanced I/O features  such as drive strength control, slew rate control, PCI compatibility,

bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and

bus-keeper features are controllable on a “per-pin” basis. A user-programmable internal oscillator is included in

MachXO3L/LF devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in

functions such as LED control, keyboard scanner and similar state machines.

The MachXO3L/LF devices also provide flexible, reliable and secure configuration from on-chip NVCM/Flash. These

devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG

test access port or through the I²C port. Additionally, MachXO3L/LF devices support dual-boot capability (using external

Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the

MachXO3L/LF family of devices. Popular logic synthesis tools provide synthesis library support for MachXO3L/LF. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route

the design in the MachXO3L/LF device. These tools extract the timing from the routing and back-annotate it into the

design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference

designs licensed free of charge, optimized for the MachXO3L/LF PLD family. By using these configurable soft core IP

cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their

productivity.

Features

• Solutions

      Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications

      Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications

      High I/O logic, lowest cost I/O, high I/O devices for I/O expansion applications

• Flexible Architecture

      Logic Density ranging from 64 to 9.4 k LUT4

      High I/O to LUT ratio with up to 384 I/O pins

• Advanced Packaging

      0.4 mm pitch: 1 k to 4 k densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm × 3.8 mm) with 28 to

      63 I/O

      0.5 mm pitch: 640 to 9.4 k LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to281 I/O

      0.8 mm pitch: 1 k to 9.4 k densities with up to 384 I/O in BGA packages

• Pre-Engineered Source Synchronous I/O

      DDR registers in I/O cells

      Dedicated gearing logic

      7:1 Gearing for Display I/O

      Generic DDR, DDRx2, DDRx4

• High Performance, Flexible I/O Buffer

      Programmable sysI/O™ buffer supports wide range of interfaces:

            LVCMOS 3.3/2.5/1.8/1.5/1.2

            LVTTL

            LVDS, Bus-LVDS, MLVDS, LVPECL

            MIPI D-PHY Emulated

            Schmitt trigger inputs, up to 0.5 V hysteresis

      Ideal for I/O bridging applications

      I/O support hot socketing

      On-chip differential termination

      Programmable pull-up or pull-down mode

• Flexible On-Chip Clocking

      Eight primary clocks

      Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

      Up to two analog PLLs per device with fractional-n frequency synthesis

            Wide input frequency range (7 MHz to 400 MHz).

• Non-volatile, Multi-time Programmable

      Instant-on

            Powers up in microseconds

      Optional dual boot with external SPI memory

      Single-chip, secure solution

      Programmable through JTAG, SPI or I2C

      MachXO3L includes multi-time programmable NVCM

      MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle for commercial/industrial devices and 10,000 for

      automotive devices

      Supports background programming of non volatile memory

• TransFR Reconfiguration

      In-field logic update while I/O holds the system state

• Enhanced System Level Support

      On-chip hardened functions: SPI, I2C, timer/counter

      On-chip oscillator with 5.5% accuracy for commercial/industrial devices

      Unique TraceID for system tracking

      Single power supply with extended operatingrange

      IEEE Standard 1149.1 boundary scan

      IEEE 1532 compliant in-system programming

• Applications

      Consumer Electronics

      Compute and Storage

      Wireless Communications

      Industrial Control Systems

      Automotive System

• Low Cost Migration Path

      Migration from the Flash based MachXO3LF to the NVCM based MachXO3L

      Pin compatible and equivalent timing

How to choose FPGA for your project?

PDF

MachXO Field Programmable Gate Array (FPGA) IC 73 9421 1200 100-LQFP

General Description

The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices

in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). 

The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column

to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize

a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-face standards. The

blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool

automatically allocates these routing resources.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-tions. The

PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are

optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in

a two-dimensional array. Only one type of block is used per row.

In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on dif-ferent

Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these

blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes

dedicated FIFO pointer and flag“hard”control logic to minimize LUT use.

The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured,

the device enters into user mode with these registers SET/RESET according to the configuration set-ting, allowing device

entering to a known state for predictable system function.

The MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices.These blocks

are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are

used to manage the frequency and phase relationships of the clocks.

Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to

the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power supplies, providing

easy integration into the overall system.

Features

• Non-volatile, Infinitely Reconfigurable

      Instant-on – powers up in microseconds

      Single chip, no external configuration memory required

      Excellent design security, no bit stream to intercept

      Reconfigure SRAM based logic in milliseconds

      SRAM and non-volatile memory programmable through JTAG port

      Supports background programming of non-volatile memory

• Sleep Mode

      Allows up to 100x static current reduction

• TransFR™ Reconfiguration (TFR)

      In-field logic update while system operates

• High I/O to Logic Density

      256 to 2280 LUT4s

      73 to 271 I/Os with extensive package options

      Density migration supported

      Lead free/RoHS compliant packaging

• Embedded and Distributed Memory

      Up to 27.6 Kbits sysMEM™ Embedded Block RAM

      Up to 7.7 Kbits distributed RAM

      Dedicated FIFO control logic

• Flexible I/O Buffer

      Programmable sysIO™ buffer supports wide range of interfaces:

      ——LVCMOS 3.3/2.5/1.8/1.5/1.2

      ——LVTTL

      ——PCI

      ——LVDS, Bus-LVDS, LVPECL, RSDS

• sysCLOCK™ PLLs

      Up to two analog PLLs per device

      Clock multiply, divide, and phase shifting

• System Level Support

      IEEE Standard 1149.1 Boundary Scan

      Onboard oscillator

      Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply

      IEEE 1532 compliant in-system programming

How to choose FPGA for your project?

PDF

CrossLink™ Field Programmable Gate Array (FPGA) IC 37 184320 5936 81-VFBGA

General Description

CrossLink™ from Lattice Semiconductor is a programmable video bridging device that supports a variety of protocols and

interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40-nm technology. It

combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC.

CrossLink supports video interfaces including MIPI® DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI,

FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, subLVDS, HiSPi and more.

Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink. By using these

configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

The Lattice Diamond® design software allows large complex designs to be efficiently implemented using CrossLink.

Synthesis library support for CrossLink devices is available for popular logic synthesis tools. The Diamond tools use the

synthesis tool output along with the constraints from its floor planning tools to place and route the design in the

CrossLink device. The tools extract the timing from the routing and back-annotate it into the design for timing verification.

Interfaces on CrossLink provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart

Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content

for mobile cameras and displays at 4 UHD and beyond.

Features

• Ultra-low power

• Sleep Mode Support

• Normal Operation – From 5 mW to 150 mW

• Ultra small footprint packages

      36-ball WLCSP (6 mm2)

      64-ball ucfBGA (12 mm2)

      80-ball ctfBGA (42 mm2)

      80-ball ckfBGA (49 mm2)

      81-ball csfBGA (20 mm2)

• Programmable architecture

      5936 LUTs

      180 Kb block RAM

      47 Kb distributed RAM

• Two hardened 4-lane MIPI D-PHY interfaces

      Transmit and receive

      6 Gb/s per D-PHY interface

• Programmable source synchronous I/O

      MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx, SLVS200 Rx, HiSPi Rx

      Up to 1200 Mb/s per I/O

      Four high-speed clock inputs

• Programmable CMOS I/O

      LVTTL and LVCMOS

      3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)

      LVCMOS differential outputs

• Flexible device configuration

      One Time Programmable (OTP) non-volatile configuration memory

      Master SPI boot from external flash

      Dual image booting supported

      I2C programming

      SPI programming

      TransFR™ I/O for simple field updates

• Enhanced system level support

      Reveal logic analyzer

      TraceID for system tracking

      On-chip hardened I2C block

• Applications examples

      Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation

      Quad MIPI CSI-2 to Single MIPI CSI-2 Aggregation

      Single MIPI DSI to Single MIPI DSI Repeater

      Single MIPI CSI-2 to Single MIPI CSI-2 Repeater

      Single MIPI DSI to Dual MIPI DSI Splitter

      Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter

      MIPI DSI to OpenLDI/FPD-Link/LVDS Translator

      OpenLDI/FPD-Link/LVDS to MIPI DSI Translator

      MIPI DSI/CSI-2 to CMOS Translator

      CMOS to MIPI DSI/CSI-2 Translator

      subLVDS to MIPI CSI-2 Translator

How to choose FPGA for your project?

PDF

XP2 Field Programmable Gate Array (FPGA) IC 201 396288 29000 256-LBGA

General Description

LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architecture

referred to as flexiFLASH.

The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with FlashBAK

embedded block memory and Serial TAG memory and design security. The parts also support Live Update technology with

TransFR, 128-bit AES Encryption and Dual-boot technologies.

The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low cost in

mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs),

pre-engineered source synchronous I/O support and enhanced sysDSP blocks.

Lattice Diamond® design software allows large and complex designs to be efficiently implemented using the LatticeXP2

family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis tools. The Diamond

software uses the synthesis tool output along with the constraints from its floor planning tools to place and route the

design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and back-annotates it into the

design for timing verification.

Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By using

these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their

productivity.

Features

• flexiFLASH™ Architecture

      Instant-on

      Infinitely reconfigurable

      Single chip

      FlashBAK™ technology

      Serial TAG memory

      Design security

• Live Update Technology

      TransFR™ technology

      Secure updates with 128 bit AES encryption

      Dual-boot with external SPI

• sysDSP™ Block

      Three to eight blocks for high performance Multiply and Accumulate

      12 to 32 18x18 multipliers

      Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers

• Embedded and Distributed Memory

      Up to 885 Kbits sysMEM™ EBR

      Up to 83 Kbits Distributed RAM

• sysCLOCK™ PLLs

      Up to four analog PLLs per device

      Clock multiply, divide and phase shifting

• Flexible I/O Buffer

      sysIO™ buffer supports:

            – LVCMOS 33/25/18/15/12; LVTTL

            – SSTL 33/25/18 class I, II

            – HSTL15 class I; HSTL18 class I, II

            – PCI

            – LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS

• Pre-engineered Source SynchronousInterfaces

      DDR / DDR2 interfaces up to 200 MHz

      7:1 LVDS interfaces support display applications

      XGMII

• Density And Package Options

      5k to 40k LUT4s, 86 to 540 I/Os

      csBGA, TQFP, PQFP, ftBGA and fpBGA packages

      Density migration supported

• Flexible Device Configuration

      SPI (master and slave) Boot Flash Interface

      Dual Boot Image supported

      Soft Error Detect (SED) macro embedded

• System Level Support

      IEEE 1149.1 and IEEE 1532 Compliant

      On-chip oscillator for initialization & general use

      Devices operate with 1.2V power supply

How to choose FPGA for your project?

PDF